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MB91121PFV

32-bit RISC Microcontroller

Fujitsu 

MB91121

• Condition code register (CCR)

S-flag : Specifies a stack pointer used as R15.

I-flag : Controls user interrupt request enable/disable.

N-flag : Indicates sign bit when division result is assumed to be in the 2’s complement format.

Z-flag : Indicates whether or not the result of division was “0”.

V-flag : Assumes the operand used in calculation in the 2’s complement format and indicates whether

or not overflow has occurred.

C-flag : Indicates if a carry or borrow from the MSB has occurred.

• System condition code register (SCR)

T-flag : Specifies whether or not to enable step trace trap.

• Interrupt level mask register (ILM)

ILM4 to ILM0 : Register for holding interrupt level mask value. The value held by this register is used as a

level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,

the interrupt request is accepted.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level High-low

0

0

0

0

0

0

High

:

:

:

:

0

1

0

0

0

15

:

:

:

:

1

1

1

1

1

31

Low

19

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