CY7C1363B Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1363B Datasheet PDF : 34 Pages
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CY7C1361B
CY7C1363B
CY7C1361B–Pin Definitions (continued)
Name
ADSC
BWE
ZZ
DQs
DQP[A:D]
MODE
VDD
VDDQ
TQFP
TQFP
BGA
fBGA
(3-Chip (2-Chip (2-Chip (3-Chip
Enable) Enable) Enable) Enable)
I/O
Description
85
85
B4
A8
Input- Address Strobe from Controller, sampled
Synchronous on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
87
87
M4
A7
Input- Byte Write Enable Input, active LOW.
Synchronous Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
64
64
T7
H11
Input- ZZ “sleep” Input, active HIGH. When
Asynchronous asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
52,53,56,57, 52,53,56,57, K6,L6,M6,
58,59,62,63, 58,59,62,63, N6,K7,L7,
68,69,72,73, 68,69,72,73, N7,P7,E6,
74,75,78,79, 74,75,78,79, F6,G6,H6,
2,3,6,7,8,9, 2,3,6,7,8,9, D7,E7,G7,
12,13,18,19, 12,13,18,19, H7,D1,E1,
22,23,24,25, 22,23,24,25, G1,H1,E2,
28,29
28,29 F2,G2,H2,
K1,L1,N1,
P1,K2,L2,
M2,N2
M11,L11,
K11,J11,
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,
F2,G2,J1,
K1,L1,M1,
J2,K2,L2
M2,
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:D] are placed
in a three-state condition.The outputs are
automatically three-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
51,80,1,30
31
51,80,1,30
31
P6,D6,D2, N11,C11,C1,
P2
N1
R3
R1
I/O-
Synchronous
Input-Static
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQs. During write sequences, DQP[A:D] is
controlled by BW[A:D] correspondingly.
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
15,41,65,91 15,41,65,91 J2,C4,J4,
R4,J6
D4,D8,E4,
E8,F4,F8,
G4,G8,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
Power Supply Power supply inputs to the core of the
device.
4,11,20,27, 4,11,20,27, A1,F1,J1,
54,61,70,77 54,61,70,77 M1,U1,
A7,F7,J7,
M7,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power Power supply for the I/O circuitry.
Supply
Document #: 38-05302 Rev. *B
Page 8 of 34
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