CY7C4215-15AXI(2011) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Lista de partido

CY7C4215-15AXI
(Rev.:2011)

256/512/1K/4K x 18 Synchronous FIFOs

Cypress Semiconductor 

CY7C4205/CY7C4215

CY7C4225/CY7C4245

Switching Waveforms (continued)

Figure 6. Read Cycle Timing

RCLK

REN

tENS

EF

tCLKH

tCLK

tCLKL

tENH

tREF

tA

NO OPERATION

tREF

Q0–Q17

OE

WCLK

tOLZ

tOE

tSKEW2 [18]

VALID DATA

tOHZ

WEN

RS

REN, WEN,

LD

EF,PAE

FF,PAF,

HF

Q0–Q17

Figure 7. Reset Timing[19]

tRS

tRSR

tRSF

tRSF

tRSF

OE = 1 [20]

OE = 0

Notes

18.

tthSKeErWis2inigs

the minimum time between a rising

edge of WCLK and the rising edge

WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the

of RCLK is less than tSKEW2, then EF may not change state until the next RCLK

current

edge.

clock

cycle.

It

the

time

between

19. The clocks (RCLK, WCLK) can be free-running during reset.

20. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

Document Number: 001-45652 Rev. *B

Page 13 of 25

[+] Feedback

Share Link: