CY7C4425-35AI Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Lista de partido

CY7C4425-35AI

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

First Data Word Latency after Reset with Simultaneous Read and Write

WCLK

tDS

D0 –D17

D0 (FIRSTVALID WRITE)

D1

D2

WEN

tENS

RCLK

tFR[L17]

tSKEW2

tREF

EF

CY7C4425/4205/4215

CY7C4225/4235/4245

D3

D4

REN

Q0 –Q17

OE

tOLZ

Empty Flag Timing

WCLK

D0 –D17

WEN

tDS

tENS

RCLK

D0

tENH

tFRL[17]

tSKEW2

tREF

EF

tA

tOE

[18]

tA

D0

D1

42X5–9

tDS

tENS

D1

tENH

tFRL[17]

tREF

tSKEW2

tREF

REN

OE

tA

Q0 –Q17

D0

42X5–10

Notes:

17. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2.

The Latency Timing applies only at the Empty Boundary (EF = LOW).

18. The first word is available the cycle after EF goes HIGH, always.

8

Share Link: