CY7C68003 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C68003 Datasheet PDF : 30 Pages
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Figure 5. Pin Assignment - TX2UL 24-Pin QFN (Top View)
CY7C68003
VSSBATT 1
NC 2
VCC 3
DATA[0] 4
DATA[1] 5
DATA[2] 6
VSS (GND)
Exposed die pad
TX2UL
18 RESET_N
17 NXT
16 STP
15 DIR
14 CLOCK
13 DATA[7]
Table 8. Pin Definitions - TX2UL 24-Pin QFN
Name Pin No. Type
Voltage
Description
ULPI Link Interface
DATA[0]
4
I/O
1.8 - 3.3 V ULPI data to/from link
DATA[1]
5
I/O
1.8 - 3.3 V ULPI data to/from link
DATA[2]
6
I/O
1.8 - 3.3 V ULPI data to/from link
DATA[3]
8
I/O
1.8 - 3.3 V ULPI data to/from link
DATA[4]
9
I/O
1.8 - 3.3 V ULPI data to/from link
DATA[5]
11
I/O
1.8 - 3.3 V ULPI data to/from link
DATA[6]
12
I/O
1.8 - 3.3 V ULPI data to/from link
DATA[7]
13
I/O
1.8 - 3.3 V ULPI data to/from link
CLOCK
14
O
1.8 - 3.3 V ULPI clock
NXT
17
O
1.8 - 3.3 V ULPI next signal
STP
16
I
1.8 - 3.3 V ULPI stop signal
DIR
15
O
1.8 - 3.3 V ULPI direction
USB
DP
22
I/O
USB
USB D-plus signal
DM
23
I/O
USB
USB D-minus signal
Misc
CS_N
7
I
1.8 - 3.3 V When CS_N is de-asserted, all pins at ULPI interface are tristated
RESET_N
18
I
1.8 - 3.3 V Device chip global reset. When RESET_N is asserted, TX2UL is in reset and
enters into the power saving mode.
XI
21
I
1.8 V
Crystal or LVCMOS single ended clock of frequency 13, 19.2, 24, or 26 MHz
XO
20
O
1.8 - 3.3 V Crystal
NC
2
-
-
No connect
POWER and GROUND
VCC
3, 19 Power
1.8 V
Low voltage supply for the digital core
VIO
10
Power 1.8 - 3.3 V Power for multi-range I/Os
VBATT
24
Power 3.0 - 5.775 V High voltage supply for USB
VSSBATT
1
GND
0
USB ground
VSS
Die Paddle GND
0
Digital ground (core and I/O)
Document Number: 001-15775 Rev. *L
Page 8 of 30
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