CY7C9235A Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C9235A Datasheet PDF : 8 Pages
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Pin Configuration
CY7C9235A
TRS_DET
TRS_FILT
SVS_EN
OE
VSS
VSS
VSS
BYPASS
DVB_EN
NC
PD9(SVS)
6 5 4 3 2 1 44 43 42 41 40
7
39
8
NC
38
9
37
10
36
11
PLCC
35
Top View
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
Q0(SC/D)
ENA_OUT
ENN
ENA
CKW
VSS
VSS
VSS
SC/D_EN
NC
NC
Pin Descriptions CY7C9235A SMPTE-259M Encoder
Name
ENA
I/O
Input
ENN
Input
BYPASS Input
TRS_DET Output
TRS_FILT Input
SVS_EN Input
Description
Enable Parallel Data. If ENA is LOW at the rising edge of CKW, the data present on the PD0−9 inputs
is latched, and routed to the Q0–9 outputs. This pin is only interpreted when DVB_EN is active (LOW).
If the CY7C9235A is only used in SMPTE-259M mode this signal should be tied to VSS.
Enable Next Parallel Data. If ENN is LOW at the rising edge of CKW, the data present on the PD0–9
inputs at the next rising edge of TXCLK is latched, and routed to the Q0–9 outputs. This pin is only
interpreted when DVB_EN is active (LOW). If the CY7C9235A is only used in SMPTE-259M mode
this signal should be tied to VSS.
Bypass SMPTE Encoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at
the rising edge of CKW (and DVB_EN is HIGH), the data latched into the input register is routed
around both the SMPTE scrambler and the NRZI encoder and presented to the output register. If
BYPASS is LOW at the rising edge of the CKW clock (and DVB_EN is HIGH), the data present in
the input register is routed through the SMPTE scrambler and NRZI encoder.
TRS Character Detected. This output indicates when a character used in the TRS sequence is
detected in the input register. If the data contains any of the reserved characters of 000–003 or
3FC–3FF in 10-bit hex, the output will be LOW for one clock period. If the character in the input
register is any other pattern (or DVB_EN is LOW) this output will remain HIGH.
TRS Character Filter. This signal controls an internal filter that converts the low-order two bits of all
TRS characters to same state as the upper eight bits. This allows a proper 30-bit TRS ID to be
generated when the CY7C9235A is operated with 8-bit or non-standard video streams. When this
signal is LOW, all characters from 000–003 are converted to 000, and all characters from 3FC–3FF
are converted to 3FF. When TRS_FILT is disabled (HIGH), all characters are passed to the scrambler
without modification. This signal has no effect when DVB_EN is active (LOW).
Send Violation Symbol Enable. This input is only valid when DVB_EN is active (LOW). If SVS_EN
is HIGH and a HIGH input is present on PD9, Q9 will also be high on a following clock cycle, forcing
the CY7B9234 serializer to generate an invalid 8B/10B character. If SVS_EN is LOW, the level
present on PD9 is ignored and Q9 is forced to a LOW state.
Document #: 38-02082 Rev. **
Page 2 of 8
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