CYRF7936 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CYRF7936 Datasheet PDF : 21 Pages
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CYRF7936
Pinouts
The CYRF7936 CyFi™ Transceiver is a Radio IC designed for low power embedded wireless applications. Combined with
Cypress’s PSoC programmable system-on-chip and a CyFi network protocol stack, CYRF7936 can be used to implement a
complete CyFi wireless system.
Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
Corner
tabs
XTAL 1
NC 2
VCC 3
NC 4
NC 5
VBAT1 6
VCC 7
VBAT2 8
NC 9
RFBIAS 10
CYRF7936
CyFi Transciever
40 lead QFN
* E- PAD Bottom Side
30 PACTL/ GPIO
29 XOUT/ GPIO
28 MISO/ GPIO
27 MOSI / SDAT
26 IRQ / GPIO
25 SCK
24 SS
23 NC
22 NC
21 NC
Table 1. Pin Description - CYRF7936 40-Pin QFN
Pin Number
Name
1
XTAL
2, 4, 5, 9, 14, 15, NC
17, 18, 20, 21, 22,
23, 31, 32, 36, 39
3, 7, 16
6, 8, 38
10
11
12
VCC
VBAT(0-2)
RFBIAS
RFP
GND
13
RFN
19
RESV
24
SS#
25
SCK
26
IRQ
27
MOSI
28
MISO
29
XOUT
30
PACTL
33
VIO
Type
I
NC
Default
I 12 MHz crystal
Connect to GND
Description
Pwr
Pwr
O
I/O
GND
IO
I
I
I
I/O
I/O
I/O
I/O
I/O
Pwr
VCC = 2.4V to 3.6V. Typically connected to VREG.
VBAT = 1.8V to 3.6V. Main supply.
O RF I/O 1.8V reference voltage
I Differential RF signal to and from antenna
Ground
I Differential RF signal to and from antenna
Must be connected to GND
I SPI enable, active LOW assertion. Enables and frames transfers.
I SPI clock
O Interrupt output (configurable active HIGH or LOW), or GPIO
I SPI data input pin (Master Out Slave In), or SDAT
Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tri-states when SPI 3PIN = 0 and SS# is deasserted.
O Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
O Control signal for external PA, T/R switch, or GPIO
IO interface voltage, 1.8–3.6V
Document Number: 001-48013 Rev*B
Page 2 of 21
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