DM74ALS646WM(2000) Ver la hoja de datos (PDF) - Fairchild Semiconductor

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DM74ALS646WM
(Rev.:2000)

Octal 3-STATE Bus Transceiver and Register

Fairchild Semiconductor 

Connection Diagram

Function Table

Inputs

Data I/O (Note 1)

G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8

Operation or Function

XX ↑XXX

Input

Not Specified Store A, B Unspecified

X X X ↑ X X Not Specified

Input

Store B, A Unspecified

HX ↑↑XX

Input

Input

Store A and B Data

H X H/L H/L X X

Input

Input

Isolation, Hold Storage

L LXXXL

Output

Input

Real-Time B Data to a Bus

L L X H/L X H

Output

Input

Stored B Data to a Bus

L HXX L X

Input

Output Real-Time A Data to B Bus

L H H/L X H X

Input

Output Stored A Data to B Bus

H = HIGH Logic Level

L = LOW Logic Level

X = Don’t Care (Either LOW or HIGH Logic Levels including transitions)

H/L = Either LOW or HIGH Logic Level excluding transitions

↑ = Positive going edge of pulse

Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data

at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

Logic Diagram

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