DM74ALS646(2000) Ver la hoja de datos (PDF) - Fairchild Semiconductor
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DM74ALS646 Datasheet PDF : 6 Pages
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Switching Characteristics
over recommended operating free air temperature range
Symbol
Parameter
Conditions
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
(with A or B LOW) (Note 5)
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
(with A or B LOW) (Note 5)
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
(with A or B HIGH) (Note 5)
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
(with A or B HIGH) (Note 5)
VCC = 4.5V to 5.5V,
CL = 50 pF,
R1 = R2 = 500Ω,
TA = Min to Max
From (Input)
Min
To (Output)
CBA or CAB
10
to A or B
CBA or CAB
5
to A or B
A or B to
5
B or A
A or B to
3
B or A
SBA or SAB
to A or B
12
SBA or SAB
to A or B
5
SBA or SAB
to A or B
6
SBA or SAB
to A or B
5
tPZH
Output Enable Time
to HIGH Level Output
G to
3
A or B
tPZL
Output Enable Time
to LOW Level Output
G to
5
A or B
tPHZ
Output Disable Time
from HIGH Level Output
G to
1
A or B
tPLZ
Output Disable Time
from LOW Level Output
G to
2
A or B
tPZH
Output Enable Time
to HIGH Level Output
DIR to
6
A or B
tPZL
Output Enable Time
to LOW Level Output
DIR to
5
A or B
tPHZ
Output Disable Time
from HIGH Level Output
DIR to
1
A or B
tPLZ
Output Disable Time
from LOW Level Output
DIR to
2
A or B
Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Max
Units
30
ns
17
ns
20
ns
12
ns
35
ns
20
ns
25
ns
20
ns
17
ns
20
ns
10
ns
16
ns
30
ns
25
ns
10
ns
16
ns
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