DM9081
Pin Description
Pin No.
Pin Name
Transceiver
100, 1
DTPO3+/-
99, 2
TPO3+/-
34, 31
TPO4+/-
33, 32
DTPO4+/-
39, 36
TPO5+/-
38, 37
DTPO5+/-
44, 41
TPO6+/-
43, 42
DTPO6+/-
49, 46
TPO7+/-
48, 47
DTPO7+/-
84, 87
TPO0+/-
85, 86
DTPO0+/-
89, 92
TPO1+/-
90, 91
DTPO1+/-
94, 97
TPO2+/-
95, 96
DTPO2+/-
52, 51
RXD7+/-
54, 53
RXD6+/-
56, 55
RXD5+/-
58, 57
RXD4+/-
60, 59
RXD3+/-
62, 61
RXD2+/-
64, 63
RXD1+/-
66, 65
RXD0+/-
70, 69
TXP1, TXN1
76, 75
TXP2, TXN2
72, 71
RXP1, RXN1
78, 77
RXP2, RXN2
74, 73
CDP1, CDN1
80, 79
CDP2, CDN2
Expansion Port
24
EXPOUT#
22
EXPIN#
23
DAT
I/O
Description
O TP Driver Outputs. The TPO+/- output generate 10Mbits/s Manchester-
encoded data. The DTPO+/- outputs are one-half bit time delayed and
inverted with respect to TPO+/-. These four outputs provide the TP drivers
with pre-distortion capability
I 10BASE-T Port Different Data Receivers
O AUI Port Different Data Drivers. The outputs are source followers that
require a 270Ω pull-down resistor
I AUI Port Differential Receive Input Pair
I AUI Port Different Collision Input Pair
O
I
I/O,Z
The assertion of this signal indicates that DM9081 is transmitting data on
DAT pins. It is active low
The assertion of this signal indicates that DM9081 is receiving data on
DAT pins. The receiving data will be broadcast to the other ports. It is
active low and is internally pulled high with a 100KΩ resistor
The DAT pins of all DM9081 chips are inter-connected. The active
DM9081 drives DAT with repeated data or jam signals in NRZ format.
The inactive DM9081 receives the repeated data or jam signals from the
DAT pin
4
Final
Version: DM9081-DS-F01
April 22, 1997