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DM9102

10/100Mbps Single Chip LAN Controller

Unspecified 

Table of Contents

General Description ................................................1

Block Diagram ........................................................1

Features .................................................................4

Pin Configuration: DM9102 QFP .............................5

Pin Description .......................................................6

- PCI Bus Interface ................................................6

- Boot ROM and EEPROM Interface ......................7

Multiplex Mode ...................................................7

Direct Mode .........................................................8

- LED Pins .............................................................9

- Network Interface ..............................................10

- Clock Pins .........................................................10

- Miscellaneous Pins............................................10

- Power Pins ........................................................11

Register Definition ................................................12

✧ PCI Configuration Registers ..............................12

Key to Default .......................................................13

Identification ID..................................................14

Command & Status............................................14

Command Register Definition ............................16

Revision ID........................................................17

Miscellaneous Function .....................................17

I/O Base Address...............................................18

Memory Mapped Base Address .........................18

Subsystem Identification ....................................19

Expansion ROM Base Address..........................19

Capabilities Pointer............................................20

Interrupt & Latency Configuration.......................20

Device Specific Configuration Register ..............20

✧ Control and Status Register (CR)......................22

Key to Default .......................................................22

1. System Control Register (CR0) .........................23

2. Transmit Descriptor Poll Demand (CR1)............24

3. Receive Descriptor Poll Demand (CR2) ............24

4. Receive Descriptor Base Address (CR3) ...........24

5. Transmit Descriptor Base Address (CR4) ..........25

6. Network Status Report Register (CR5)..............25

7. Network Operation Register (CR6) ....................27

8. Interrupt Mask Register (CR7)...........................29

9. Statistical Counter Register (CR8).....................30

10. PROM & Management Access Register (CR9) 31

11. Programming ROM Address Register (CR10) .32

12. General Purpose Timer Register (CR11) .........32

2

DM9102

10/100Mbps Single Chip LAN Controller

13. PHY Status Register (CR12)........................... 32

14. Frame Access Register................................... 33

15. Frame Data Register (CR14) .......................... 33

16. Watching & Jabber Timer Register (CR15) ..... 33

✧ PHY Management Register Set ........................ 34

Key To Default ..................................................... 34

Basic Mode Control Register (BMCR)

- Register 0 .......................................................... 35

Basic Mode Status Register (BMSR)

- Register 1 .......................................................... 36

PHY ID Identifier Register #1 (PHYIDR1)

- Register 2 .......................................................... 37

PHY ID Identifier Register #2 (PHYIDR2)

- Register 3 .......................................................... 37

Auto-negotiation Advertisement Register (ANAR)

- Register 4 .......................................................... 37

Auto-negotiation Link Partner Ability Register

(ANLPAR) - Register 5 ......................................... 38

Auto-negotiation Expansion Register (ANER)

- Register 6 .......................................................... 39

DAVICOM Specified Configuration Register (DSCR)

- Register 16......................................................... 39

DAVICOM Specified Configuration and Status

Register (DSCSR) - Register 17 ........................... 40

10Base-T Configuration/Status (10BTSCRCSR)

- Register 18......................................................... 41

Functional Description .......................................... 42

✧ System Buffer Management .............................. 42

1. Overview .......................................................... 42

2. Data Structure and Descriptor List .................... 42

3. Buffer Management: Ring Structure Method ..... 42

4. Buffer Management: Chain Structure Method ... 43

5. Descriptor List: Buffer Descriptor Format .......... 43

(a). Receive Descriptor Format ............................. 43

(b). Transmit Descriptor Format ............................ 45

Final

Version: DM9102-DS-F03

August 30, 2000

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