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DM9000B

Ethernet Controller With General Processor Interface

Davicom Semiconductor, Inc. 

DM9000B

Ethernet Controller with General Processor Interface

6. Vendor Control and Status Register Set

The DM9000B implements several control and status

registers, which can be accessed by the host. These CSRs

are byte aligned. All CSRs are set to their default values by

hardware or software reset unless they are specified

Register

NCR

NSR

TCR

TSR I

TSR II

RCR

RSR

ROCR

BPTR

FCTR

FCR

EPCR

EPAR

EPDRL

EPDRH

WCR

PAR

MAR

GPCR

GPR

TRPAL

TRPAH

RWPAL

RWPAH

VID

PID

CHIPR

TCR2

OCR

SMCR

ETXCSR

TCSCR

RCSCSR

MPAR

LEDCR

BUSCR

INTCR

SCCR

Description

Network Control Register

Network Status Register

TX Control Register

TX Status Register I

TX Status Register II

RX Control Register

RX Status Register

Receive Overflow Counter Register

Back Pressure Threshold Register

Flow Control Threshold Register

RX Flow Control Register

EEPROM & PHY Control Register

EEPROM & PHY Address Register

EEPROM & PHY Low Byte Data Register

EEPROM & PHY High Byte Data Register

Wake Up Control Register (in 8-bit mode)

Physical Address Register

Multicast Address Register

General Purpose Control Register (in 8-bit mode)

General Purpose Register

TX SRAM Read Pointer Address Low Byte

TX SRAM Read Pointer Address High Byte

RX SRAM Write Pointer Address Low Byte

RX SRAM Write Pointer Address High Byte

Vendor ID

Product ID

CHIP Revision

TX Control Register 2

Operation Control Register

Special Mode Control Register

Early Transmit Control/Status Register

Transmit Check Sum Control Register

Receive Check Sum Control Status Register

MII PHY Address Register

LED Pin Control Register

Processor Bus Control Register

INT Pin Control Register

System Clock Turn ON Control Register

Offset

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H-15H

16H-1DH

1EH

1FH

22H

23H

24H

25H

28H-29H

2AH-2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

38H

39H

50H

Default value

after reset

00H

00H

00H

00H

00H

00H

00H

00H

37H

38H

00H

00H

40H

XXH

XXH

00H

Determined by

EEPROM

XXH

01H

XXH

00H

00H

00H

0CH

0A46H

9000H

1AH

00H

00H

00H

00H

00H

00H

00H

00H

01H

00H

00H

Final

13

Version: DM9000B-13-DS-F02

June 4, 2009

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