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DM9006 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

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DM9006 Datasheet PDF : 76 Pages
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DM9006
2-port Switch with Processor Interface
3. FEATURES
‰ Ethernet Switch with two 10/100Mb PHY, and a flexible 8-bit or 16-bit general processor
bus interface
‰ Store and Forward switching approach
‰ Support HP Auto-MDIX
‰ Support up-to 1K Unicast MAC addresses
‰ Support IEEE 802.3x Flow Control in Full-duplex mode
‰ Support Back Pressure Flow Control in Half-duplex mode
‰ Per port supports ingress or egress bandwidth rate control
‰ Support Broadcast/Multicast Storm Suppression
‰ Support maximum packet length up to 1536(default)/2032 bytes
‰ Support head of Line (HOL) blocking prevention
‰ Support MIB counters for diagnostic
‰ General processor bus is slave architecture
‰ General processor bus driving capability is adjustable
‰ General processor bus supports TCP/UDP/IPv4 checksum offload
‰ EEPROM interface for power up configuration
‰ Support EEPROM 93C46/93C56 with auto-detecting
‰ Driving capability of TXD/TXE of MII is adjustable
‰ Per port supports 4 level priority queues by Port-based, 802.1p VLAN, and IP TOS priority.
The priority queue can be set at WRR(Weighted Round Robin) or Strictly(High priority
queue first)
‰ Support 802.1Q VLAN up-to 16 VLAN group.
‰ Support VLAN ID tag/untag options
‰ MAC Address Table is accessible
‰ Support 256-entry multicast address table
‰ Support port security function
‰ Support 32 entry hardware-based IGMP Snooping V1, V2
‰ uP data driving capability adjustable
‰ 64-pin LQFP 1.8V internal core, 3.3V I/O with 5V tolerant
‰ Support Lead-Free and Halogen–Free
Preliminary datasheet
11
DM9006-13-DS-P01
September 1, 2009

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