DM9013 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

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DM9013

10/100 Mbps 3-port Ethernet Switch Controller with General Processor Interface

Davicom Semiconductor, Inc. 

DM9013

3-port switch with Processor Interface

P_CTRL Per Port Control Data Register

61H

00H

P_STUS Per Port Status Data Register

62H

00H

P_RATE Per Port Ingress and Egress Rate Control Register

66H

00H

P_BW

Bandwidth Control Register

67H

00H

P_UNICAST Per Port Block Unicast ports Control Register

68H

00H

P_MULTI Per Port Block Multicast ports Control Register

69H

00H

P_BCAST Per Port Block Broadcast ports Control Register

6AH

00H

P_UNKNWN Per Port Block Unknown ports Control Register

6BH

00H

P_PRI Per Port Priority Queue Control Register

6DH

00H

VLAN_TAGL Per Port VLAN Tag Low Byte Register

6EH

01H

VLAN_TAGH Per Port VLAN Tag High Byte Register

6FH

00H

P_MIB_IDX Per Port MIB counter Index Register

80H

00H

MIB_DAT MIB counter Data Register bit 0~7

81H

00H

MIB_DAT MIB counter Data Register bit 8~15

82H

00H

MIB_DAT MIB counter Data Register bit 16~23

83H

00H

MIB_DAT MIB counter Data Register bit 24~31

84H

00H

PVLAN Port-based VLAN mapping table registers

B0-BFH

0FH

TOS_MAP TOS Priority Map Register

C0-CFH

00H~FFH

VLAN_MAP VLAN priority Map Register

D0-D1H

50H,FAH

MRCMDX Memory Data Pre-Fetch Read Command Without Address F0H

XXH

Increment Register

MRCMD Memory Data Read Command With Address Increment F2H

XXH

Register

MRRL

Memory Data Read address Register Low Byte

F4H

00H

MRRH Memory Data Read address Register High Byte

F5H

00H

MWCMDX Memory Data Write Command Without Address Increment F6H

XXH

Register

MWCMD Memory Data Write Command With Address Increment F8H

XXH

Register

MWRL Memory Data Write address Register Low Byte

FAH

00H

MWRH Memory Data Write address Register High Byte

FBH

00H

TXPLL TX Packet Length Low Byte Register

FCH

XXH

TXPLH TX Packet Length High Byte Register

FDH

XXH

ISR

Interrupt Status Register

FEH

00H

IMR

Interrupt Mask Register

FFH

00H

Key to Default

In the register description that follows, the default column

E = default value from EEPROM

takes the form:

T = default value from strap pin

<Reset Value>, <Access Type>

<Access Type>:

Where:

RO = Read only

<Reset Value>:

RW = Read/Write

1

Bit set to logic one

R/C = Read and Clear

0

Bit set to logic zero

RW/C1=Read/Write and Cleared by write 1

X

No default value

WO = Write only

P = power on reset default value

Reserved bits are shaded and should be written with 0.

H = hardware reset command default value

Reserved bits are undefined on read access.

S = software reset default value

20

Preliminary datasheet

DM9013-15-DS-P03

April 9, 2009

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