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DM9161

10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver

Davicom Semiconductor, Inc. 

DM9161

10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver

34

RXCLK

O, Receive Clock

/SCRAMEN Z, The received clock provides the timing reference for the transfer of the

/10BTSER

LI RXDV, RXD, and RXER. RXCLK is provided by PHY. The PHY may

(U) recover the RXCLK reference from the received data or it may derive the

RXCLK reference from a nominal clock

25MHz in 100Mbps MII mode, 2.5MHz in 10Mbps MII mode, 10MHz in

10Mbps GPSI (7-Wired) mode

SCRAMEN 10BTSER only support for forced 100M mode or 10M mode;

not support for auto-negotiation mode (power up reset latch input)

0 = Bypass scramble in 100M mode, GPSI (7-Wired) mode in 10M mode

1 = Enable scramble (default) in 100M mode, MII mode in 10M mode

35

CRS

O, Carrier Sense Detect/ PHYAD[4]

/PHYAD[4]

Z, Asserted high to indicate the presence of carrier due to receive or transmit

LI activities in half-duplex mode of 10BASE-T or 100BASE-TX. In repeater

(D) mode or full-duplex mode, this signal is asserted high to indicate the

presence of carrier due to receive activity only

This pin is also used as PHYAD [4] (power up reset latch input)

PHY address sensing input pin

36

COL

O, Collision Detection

/RMII

Z, Asserted high to indicate the detection of the collision conditions in 10Mbps

LI and 100Mbps half-duplex mode. In full-duplex mode, this signal is always

(D) logical 0.

Reduced MII enable:

This pin is also used to select Normal MII or Reduced MII. (power up reset

latch input)

0= Normal MII (default)

1= Reduced MII

This pin is always pulled low except used as reduced MII

37

RXDV

O, Receive Data Valid

/TESTMODE Z, Asserted high to indicate that the valid data is presented on the RXD [0:3]

LI Test mode control pin (power up reset latch input)

(D) 0 = normal operation (default)

1 = enable test mode

38

RXER/RXD[4] O, Receive Data Error/The Fifth RXD Data Bit of the 5B Symbol

/RPTR

Z, Asserted high to indicate that an invalid symbol has been detected

LI In decoder bypass mode (bypass BP4B5B), RXER becomes RXD [4], the

(D) fifth RXD data bit of the 5B symbol

This pin is also used to select Repeater or Node mode. (power up reset

latch input)

0 = Node Mode (default)

1 = Repeater Mode

31

RXEN

I Receive Enable

Active high enables receive signals RXD [0:3], RXCLK, RXDV and RXCLK.

Active low on this input tri-states these output pins. In node application, this

pin should be pulled high. In repeater application, this pin may be

connected to a repeater controller

40

RESET#

I Reset

Active low input that initializes the DM9161.

Final

7

Version: DM9161-DS-F05

September 10, 2008

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