datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga

DS1644L-120 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

Número de pieza
componentes Descripción
Lista de partido
DS1644L-120
Dallas
Dallas Semiconductor -> Maxim Integrated Dallas
DS1644L-120 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
DS1644LPM
DS1644LPM
Nonvolatile Timekeeping RAM
FEATURES
Upward compatible with the DS1643AL Timekeeping
RAM to achieve higher RAM density
Integrated NV SRAM, real time clock, crystal, power–
fail control circuit and lithium energy source
Low profile socketable module
– 255 mil package height
Clock registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
Totally nonvolatile with over 10 years of operation in
the absence of power
Access time of 120 ns and 150 ns
Quartz accuracy ±1 minute a month @ 25°C, factory
calibrated
BCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to
2100
Power–fail write protection allows for ±10% VCC pow-
er supply tolerance
ORDERING INFORMATION
DS1644L–XXX Low Profile Module
–120 120 ns access
–150 150 ns access
DESCRIPTION
The DS1644L is a low profile module that requires a
PLCC surface mountable socket and is functionally
equivalent to the DS1644. The DS1644L is a 32K x 8
nonvolatile static RAM with a full function real time clock
which are both accessible in a Byte–wide format. The
real time clock information resides in the eight upper-
most RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in
24 hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC
clock registers are double buffered to avoid access of in-
PIN ASSIGNMENT
NC
1
NC
2
NC
3
PFO
4
VCC
5
WE
6
OE
7
CE
8
DQ7
9
DQ6
10
DQ5
11
DQ4
12
DQ3
13
DQ2
14
DQ1
15
DQ0
16
GND
17
34
NC
33
NC
32
A14
31
A13
30
A12
29
A11
28
A10
27
A9
26
A8
25
A7
24
A6
23
A5
22
A4
21
A3
20
A2
19
A1
18
A0
34–PIN LOW PROFILE MODULE
PIN DESCRIPTION
A0–A14
– Address Input
CE
– Chip Enable
OE
– Output Enable
WE
– Write Enable
VCC
GND
– +5 Volts
– Ground
DQ0-DQ7
– Data Input/Output
NC
– No Connection
PFO
– Power Fail Output
correct data that can occur during clock update cycles.
The double buffered system also prevents time loss as
the timekeeping countdown continues unabated by ac-
cess to time register data. The DS1644L also contains
its own power–fail circuitry which deselects the device
when the VCC supply is in an out–of–tolerance condi-
tion. This feature prevents loss of data from unpredict-
able system operation brought on by low VCC as errant
access and update cycles are avoided.
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041697 1/11

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]