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DS1644LPM

Nonvolatile Timekeeping RAM

Dallas Semiconductor -> Maxim Integrated 

DS1644LPM

DS1644L REGISTER MAP – BANK1 Table 2

DATA

ADDRESS

B7

B6

B5

B4

B3

B2

B1

B0

7FFF

–

–

–

–

–

–

–

–

FUNCTION

YEAR 00–99

7FFE

X

X

X

–

–

–

–

–

MONTH 01–12

7FFD

X

X

–

–

–

–

–

–

DATE 01–31

7FFC

X

FT

X

X

X

–

–

–

DAY

01–07

7FFB

X

X

–

–

–

–

–

–

HOUR 00–23

7FFA

X

–

–

–

–

–

–

–

MINUTES 00–59

7FF9

OSC

–

–

–

–

–

–

– SECONDS 00–59

7FF8

W

R

X

X

X

X

X

X CONTROL A

OSC = STOP BIT

W = WRITE BIT

R = READ BIT

X = UNUSED

FT = FREQUENCY TEST

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1644L is in the read mode whenever WE (write

enable) is high, and CE (chip enable) is low. The device

architecture allows ripple-through access to any of the

address locations in the NV SRAM. Valid data will be

available at the DQ pins within tAA after the last address

input is stable, providing that the CE and OE access

times and states are satisfied. If CE or OE access times

are not met, valid data will be available at the latter of

chip enable access (tCEA) or at output enable access

time (tOEA). The state of the data input/output pins (DQ)

is controlled by CE and OE. If the outputs are activated

before tAA, the data lines are driven to an intermediate

state until tAA. If the address inputs are changed while

CE and OE remain valid, output data will remain valid for

output data hold time (tOH) but will then go indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1644L is in the write mode whenever WE and

CE are in their active state. The start of a write is refer-

enced to the latter occurring high to low transition of WE

or CE. The addresses must be held valid throughout the

cycle. CE or WE must return inactive for a minimum of

tWR prior to the initiation of another read or write cycle.

Data in must be valid tDS prior to the end of write and re-

main valid for tDH afterward. In a typical application, the

OE signal will be high during a write cycle. However,

OE can be active provided that care is taken with the

data bus to avoid bus contention. If OE is low prior to

WE transitioning low the data bus can become active

with read data defined by the address inputs. A low tran-

sition on WE will then disable the outputs tWEZ after WE

goes active.

041697 4/11

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