DS1854 Ver la hoja de datos (PDF) - Maxim Integrated
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DS1854 Datasheet PDF : 22 Pages
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Dual Temperature-Controlled Resistors with
Two Monitors
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SCL Clock Frequency
Bus Free Time Between STOP and
START Condition
Hold Time (Repeated)
START Condition
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time
Data Setup Time
Start Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
EEPROM Write Time
SYMBOL
CONDITIONS
Fast mode (Note 9)
fSCL
Standard mode (Note 9)
tBUF
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Notes 9, 10)
tHD:STA Standard mode (Notes 9, 10)
tLOW
Fast mode (Note 9)
Standard mode (Note 9)
tHIGH
Fast mode (Note 9)
Standard mode (Note 9)
Fast mode (Notes 9, 11, 12)
tHD:DAT Standard mode (Notes 9, 11, 12)
Fast mode (Note 9)
tSU:DAT Standard mode (Note 9)
Fast mode (Note 9)
tSU:STA Standard mode (Note 9)
Fast mode (Note 13)
tR
Standard mode (Note 13)
Fast mode (Note 13)
tF
Standard mode (Note 13)
Fast mode
tSU:STO
Standard mode
CB (Note 13)
tW
(Note 14)
MIN TYP
0
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
0
100
250
0.6
4.7
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
0.6
4.0
10
MAX
400
100
UNITS
kHz
µs
µs
µs
µs
0.9
µs
ns
µs
300
ns
1000
300
ns
300
µs
400
pF
ms
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All voltages are referenced to ground.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels.
The maximum voltage the MON inputs will read is approximately 2.5V, even if the voltage on the inputs are
greater than 2.5V.
This voltage is defining the maximum range of the analog-to-digital converter and not the maximum
VCC voltage.
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
See the Typical Operating Characteristics.
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns
before the SCL line is released.
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