DS1882 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Lista de partido

DS1882

Dual Log Audio Digital Potentiometer

Maxim Integrated 

Dual Log Audio Digital Potentiometer

I2C Interface for the DS1882

The CE pin serves as a communication enable pin.

When active (CE = 0), the inputs SDA and SCL are rec-

ognized by the device. If inactive (CE = 1), pins SDA

and SCL are disabled, making I2C communication

impossible.

Three pins, A0, A1, A2, serve as slave address inputs.

For multidrop configurations, they allow eight such

devices to be addressed by the same I2C bus. If the

I2C address matches the hardware levels of these bits,

the DS1882 is allowed to receive communications from

the I2C bus.

The I2C slave address byte is shown below. This is the

first byte transmitted from the master to the DS1882.

The upper nibble value is fixed to 0101. Bit values A2,

A1, and A0 are determined by the states of the corre-

sponding pins. The LSB, R/W, determines whether a

read or write will be performed.

The next byte to be transmitted is the Command Byte

(see the Command Byte section for details).

0

1

MSB

SLAVE ADDRESS BYTE

0

1

A2

A1

A0

R/W

LSB

Reading Pot Values

As shown in Figure 1, the DS1882 provides one read

command operation. This operation allows the user to

read both Potentiometer Wiper Setting Registers and

the Configuration Register. To initiate a read operation,

the R/W bit of the slave address byte is set to 1.

Communication to read the DS1882 begins with a

START condition, which is issued by the master device.

The slave address byte sent from the master device fol-

lows the START condition. Once a matching slave

address byte has been received by the DS1882, the

DS1882 responds with an acknowledge. The master

can then begin to receive data. The value of the wiper

of Potentiometer 0 is the first returned from the DS1882.

It is then followed by the value of Potentiometer 1 and

then the value of the Configuration Register. Once the 8

bits of the Configuration Register have been sent, the

master needs to issue an acknowledge, unless it is the

last byte to be read, in which case the master issues a

not acknowledge. If desired, the master may stop the

communication transfer at this point by issuing the

STOP condition after the not acknowledge. However, if

the value of the three registers is needed again, the

transfer can continue by clocking the 8 bits of the

Potentiometer 0 value as described above.

SLAVE ADDRESS

BYTE

MSB

LSB

0

1

0

1

A

2

A

1

A

0

1

R/W = 1

Figure 1. Read Protocol

READ PROTOCOL

COMMAND

BYTE

MSB

LSB

COMMAND

BYTE

MSB

LSB

00

POT-0

01

POT-1

DATA BYTES ARE READ IN THE ORDER SHOWN ABOVE.

MSB

10

COMMAND

BYTE

LSB

CONFIG

REG

____________________________________________________________________ 11

Share Link: