DS2148 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2148

5V E1/T1/J1 Line Interface

Dallas Semiconductor -> Maxim Integrated 

TRANSMIT LOGIC Figure 3-3

CCR1.6

CCR3.3 CCR3.4

DS2148/Q48

To

Remote

Loopback

CCR3.1

OR

Gate

1

BPV

mux

Insert

CCR2.2

B8ZS/

HDB3

Coder

CCR3.0

Logic

Error

Insert

PRBS Generator

mux

Loop Code Generator

OR

Gate

Routed to

All Blocks

0

0

mux

RCLK

1

CCR1.1

0

mux

1

OR

Gate

AND

Gate

CCR1.2

CCR1.0

JACLK

(derived

from

MCLK)

Loss Of Transmit

Clock Detect

To LOTC Output Pin

SR.5

Clock

Invert

CCR2.1

tx bd

TPOS

TNEG

TCLK

4. PIN DESCRIPTION

The DS2148 can be controlled in a parallel port mode, a serial port mode, or a hardware mode (Table 4-1,

4-2, and 4-3). The parallel and serial port modes are described in Section 3, and the hardware mode is

described below.

BUS INTERFACE SELECTION Table 4-1

BIS1

BIS0

PBTS

0

0

0

0

0

1

0

1

0

0

1

1

1

0

-

1

1

-

BUS INTERFACE TYPE

Muxed Intel

Muxed Motorola

Nonmuxed Intel

Nonmuxed Motorola

Serial Port

Hardware

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