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DTC115EET1 Datasheet PDF : 10 Pages
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DTC114EET1 Series
Bias Resistor Transistor
NPN Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base−emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC−75/SOT−416 package which is designed for low power surface
mount applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• The SC−75/SOT−416 Package Can be Soldered Using Wave or
Reflow
• The Modified Gull−Winged Leads Absorb Thermal Stress During
Soldering Eliminating the Possibility of Damage to the Die
• Available in 8 mm, 7 inch/3000 Unit Tape & Reel
• Pb−Free Packages are Available
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
Collector Current
IC
100 mAdc
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
THERMAL CHARACTERISTICS
Rating
Symbol Value Unit
Total Device Dissipation,
FR−4 Board (Note 1) @ TA = 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient (Note 1)
PD
RqJA
200
mW
1.6 mW/°C
600 °C/W
Total Device Dissipation,
FR−4 Board (Note 2) @ TA = 25°C
Derate above 25°C
Thermal Resistance,
Junction−to−Ambient (Note 2)
PD
RqJA
300
mW
2.4 mW/°C
400 °C/W
Junction and Storage Temperature Range TJ, Tstg −55 to
°C
+150
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 × 1.0 Inch Pad
© Semiconductor Components Industries, LLC, 2005
1
January, 2005 − Rev. 6
http://onsemi.com
NPN SILICON
BIAS RESISTOR TRANSISTORS
PIN 1
R1
BASE
(INPUT) R2
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
MARKING
DIAGRAM
3
2
1
SC−75/SOT−416
CASE 463
STYLE 1
xx M
xx = Specific Device Code
M = Date Code
ORDERING INFORMATION
See detailed ordering, marking, and shipping information in
the package dimensions section on page 2 of this data sheet.
Publication Order Number:
DTC114EET1/D
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