RF2162 Ver la hoja de datos (PDF) - RF Micro Devices
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RF2162 Datasheet PDF : 10 Pages
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Preliminary
RF2162
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pkg
Base
Function
GND
GND1
GND1
RF IN
Description
Interface Schematic
Ground connection. Connect to package base ground. This ground
should be isolated from the backside ground contact on top metal layer.
Ground for stage 1. Keep traces physically short and connect immedi-
ately to ground plane for best performance. This ground should be iso-
lated from the backside ground contact on top metal layer.
Same as Pin 2.
RF input. An external DC blocking capacitor is required if this port is
connected to a DC path to ground or a DC voltage.
VCC1
VREG1
VMODE
VREG2
GND
GND
RF OUT
RF OUT
RF OUT
2FO
VCC BIAS
VCC1
VCC1
GND
RF IN
From Bias
Stages GND1
Enable voltage for first stage. When this pin is “low”, all circuits are shut
off. When this pin is 2.8V, all circuits are operating normally. VREG
requires a regulated 2.8V for the amplifier to operate properly over all
specified temperature and voltage ranges. A dropping resistor from a
higher regulated voltage may be used to provide the required 2.8V. A
100pF high frequency bypass capacitor is recommended.
This is an analog bias current control pin. The range is 0V for minimum
bias to 3.0 for maximum bias.
Enable voltage for second or output stage. When this pin is “low”, all cir-
cuits are shut off. When this pin is 2.8V, all circuits are operating nor-
mally. VREG requires a regulated 2.8V for the amplifier to operate
properly over all specified temperature and voltage ranges. A dropping
resistor from a higher regulated voltage may be used to provide the
required 2.8V. A 100pF high frequency bypass capacitor is recom-
mended.
Bias circuitry ground. See application schematic.
Ground connection. Connect to package base ground. This ground
should be isolated from the backside ground contact on top metal layer.
RF output and power supply for the output stage. The bias for the out-
put stage is provided through this pin and pin 13. An external matching
network is required to provide the optimum load impedance; see the
application schematics for details.
RF OUT
From Bias
Stages
Same as pin 10.
See pin 10.
Same as pin 10.
Harmonic trap. This pin connects to the RF output but is used for pro-
viding a low impedance to the second harmonic of the operating fre-
quency. An inductor or transmission line resonating with an on chip
capacitor at 2fo is required at this pin.
Power supply for bias circuitry. A 100pF high frequency bypass capaci-
tor is recommended.
Interstage tuning and bias supply for first stage.
Interstage tuning and bias supply for first stage.
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias. The pad should have a short thermal path to the ground
plane.
Rev A19 060208
2-229
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