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EBD11UD8ABDA Ver la hoja de datos (PDF) - Elpida Memory, Inc

Número de pieza
componentes Descripción
Lista de partido
EBD11UD8ABDA
Elpida
Elpida Memory, Inc Elpida
EBD11UD8ABDA Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
EBD11UD8ABDA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
2
Memory type
0 0 0 0 0 1 1 1 07H
3
Number of row address
0 0 0 0 1 1 0 1 0DH
4
Number of column address
0 0 0 0 1 0 1 1 0BH
5
Number of DIMM ranks
0 0 0 0 0 0 1 0 02H
6
Module data width
0 1 0 0 0 0 0 0 40H
7
Module data width continuation
0 0 0 0 0 0 0 0 00H
8
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
9
DDR SDRAM cycle time, CL = X
-6B
0 1 1 0 0 0 0 0 60H
-7A,-7B
0 1 1 1 0 1 0 1 75H
10
SDRAM access from clock (tAC)
-6B
-7A, -7B
0 1 1 1 0 0 0 0 70H
0 1 1 1 0 1 0 1 75H
11
DIMM configuration type
0 0 0 0 0 0 0 0 00H
12
Refresh rate/type
1 0 0 0 0 0 1 0 82H
13
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
14
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
15
Minimum clock delay back-to-back
0 0 0 0 0 0 0 1 01H
column access
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes: /CAS latency 0 0 0 0 1 1 0 0 0CH
19
SDRAM device attributes: /CS latency 0 0 0 0 0 0 0 1 01H
20
SDRAM device attributes: /WE latency 0 0 0 0 0 0 1 0 02H
21
SDRAM module attributes
0 0 1 0 0 0 0 0 20H
22
SDRAM device attributes: General
1 1 0 0 0 0 0 0 C0H
Minimum clock cycle time at
23
CL = X –0.5
-6B, -7A
0 1 1 1 0 1 0 1 75H
-7B
1 0 1 0 0 0 0 0 A0H
Maximum data access time (tAC) from
24
clock at CL = X –0.5
0 1 1 1 0 0 0 0 70H
-6B
-7A, -7B
0 1 1 1 0 1 0 1 75H
25 to 26
27
Minimum row precharge time (tRP)
-6B
-7A, -7B
0 0 0 0 0 0 0 0 00H
0 1 0 0 1 0 0 0 48H
0 1 0 1 0 0 0 0 50H
Comments
128 bytes
256 bytes
DDR SDRAM
13
11
2
64 bits
0
SSTL2.5V
CL = 2.5*1
0.70ns*1
0.75ns*1
None
7.6µs
Self refresh
×8
Not used
1 CLK
2,4,8
4
2, 2.5
0
1
Unbuffered
VDD ± 0.2V
CL = 2*1
0.70ns*1
0.75ns*1
18ns
20ns
Data Sheet E0287E70 (Ver. 7.0)
5

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