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EBE10RD4AEFA-6

1GB Registered DDR2 SDRAM DIMM

Elpida Memory, Inc 

EBE10RD4AEFA-6

DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)

Parameter

Symbol Grade

max.

Unit

Test condition

Operating current

(ACT-PRE)

IDD0

Operating current

(ACT-READ-PRE)

IDD1

EPrecharge power-down

standby current

IDD2P

OPrecharge quiet standby

L current

IDD2Q

Idle standby current

IDD2N

IDD3P-F

Active power-down standby

current

IDD3P-S

Active standby current

IDD3N

Operating current

(Burst read operating)

IDD4R

Operating current

(Burst write operating)

IDD4W

2570

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

mA

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

2920

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

mA

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

all banks idle;

tCK = tCK (IDD);

750

mA

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

1020

all banks idle;

tCK = tCK (IDD);

mA

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

1200

P1290

1020

ro1850

d 4270

uct 4090

all banks idle;

tCK = tCK (IDD);

mA

CKE is H, /CS is H;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

all banks open;

mA

tCK = tCK (IDD);

CKE is L;

Fast PDN Exit

MRS(12) = 0

Other control and

address bus inputs are

mA

STABLE;

Data bus inputs are

Slow PDN Exit

MRS(12) = 1

FLOATING

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

tRP = tRP (IDD);

mA

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are

SWITCHING;

Data bus inputs are SWITCHING

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP

mA

(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

mA

tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Data Sheet E0740E11 (Ver. 1.1)

11

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