EBE21AD4AGFA-4A-E Ver la hoja de datos (PDF) - Elpida Memory, Inc

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EBE21AD4AGFA-4A-E

2GB Registered DDR2 SDRAM DIMM

Elpida Memory, Inc 

EBE21AD4AGFA

Pin Description

Pin name

Function

A0 to A13

A10 (AP)

Address input

Row address

Column address

Auto precharge

A0 to A13

A0 to A9, A11

BA0, BA1

Bank select address

DQ0 to DQ63

Data input/output

CB0 to CB7

Check bit (Data input/output)

/RAS

Row address strobe command

/CAS

Column address strobe command

/WE

Write enable

/CS0, /CS1

Chip select

CKE0, CKE1

Clock enable

CK0

Clock input

/CK0

Differential clock input

DQS0 to DQS17, /DQS0 to /DQS17

Input and output data strobe

SCL

Clock input for serial PD

SDA

Data input/output for serial PD

SA0 to SA2

Serial address input

VDD

Power for internal circuit

VDDSPD

Power for serial EEPROM

VREF

Input reference voltage

VSS

Ground

ODT0, ODT1

/RESET

Par_In*2

/Err_Out*2

ODT control

Reset pin (forces register and PLL inputs low) *1

Parity bit for the address and control bus

Parity error found on the address and control bus

NC

No connection

Notes: 1. Reset pin is connected to both OE of PLL and reset to register.

2. /Err_Out (Pin No. 55) and Par_In (Pin No. 68) are for optional function to check address and command

parity.

Preliminary Data Sheet E0866E11 (Ver. 1.1)

4

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