LTC1288 Ver la hoja de datos (PDF) - Linear Technology
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LTC1288 Datasheet PDF : 24 Pages
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LTC1285/LTC1288
APPLICATION INFORMATION
Several things must be taken into account to achieve such
a low power consumption.
Shutdown
The LTC1285/LTC1288 are equipped with automatic shut-
down features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference
input becomes high impedance at the end of each conver-
sion leaving the CLK running to clock out the LSB first data
or zeroes (see Figures 1 and 2). If the CS is not running rail-
to-rail, the input logic buffer will draw current. This current
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
ground when it is low and to supply voltage when it is high.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK input have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high; they can continue to run without
drawing current.
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the
9
TA = 25°C
8 VCC = 2.7V
7 VREF = 2.5V
6
5
4
CS = 0
3
(AFTER CONVERSION)
2
1
0.002
0
1
CS = VCC
20 40 60 80 100 120
FREQUENCY (kHz)
LTC1285/88 • TPC03
Figure 5. Shutdown Current with CS High is 1nA Typically,
Regardless of the Clock. Shutdown Current with CS = Ground
Varies From 1µA at 1kHz to 9µA at 120kHz
lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
LSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1µA at 1kHz to 9µA at 120kHz. When
CS = VCC, the logic is gated off and no supply current is
drawn regardless of the clock frequency.
DOUT Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can add more than 16.2µA to the supply current at a
120kHz clock frequency. An extra 16.2µA or so of current
goes into charging and discharging the load capacitor. The
same goes for digital lines driven at a high frequency by
any logic. The C × V × f currents must be evaluated and the
troublesome ones minimized.
OPERATING ON OTHER THAN 3V SUPPLIES
Both the LTC1285 and the LTC1288 operate from a 2.7V
to 6V supply. To operate the LTC1285/LTC1288 on other
than 3V supplies a few things must be kept in mind.
Input Logic Levels
The input logic levels of CS, CLK and DIN are made to
meet TTL on a 3V supply. When the supply voltage varies,
the input logic levels also change. For the LTC1285/
LTC1288 to sample and convert correctly, the digital
inputs have to be in the proper logical low and high levels
relative to the operating supply voltage (see typical curve
of Digital Input Logic Threshold vs Supply Voltage). If
achieving micropower consumption is desirable, the
digital inputs must go rail-to-rail between supply voltage
and ground (see ACHIEVING MICROPOWER PERFOR-
MANCE section).
Clock Frequency
The maximum recommended clock frequency is 120kHz
for the LTC1285/LTC1288 running off a 3V supply. With
the supply voltage changing, the maximum clock fre-
quency for the devices also changes (see the typical curve
14
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