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LTC1283CN
(Rev.:RevB)

3V Single Chip 10-Bit Data Acquisition System

Linear Technology 

LTC1283

APPLICATI S I FOR ATIO

The LTC1283 is a 3V data acquisition component which

contains the following functional blocks:

1. 10-bit successive approximation capacitive

A/D converter

2. Analog multiplexer (MUX)

3. Sample-and-hold (S&H)

4. Synchronous, full duplex serial interface

5. Control and timing logic

DIGITAL CONSIDERATIONS

1. Serial Interface

The LTC1283 communicates with microprocessors and

other external circuitry via a synchronous, full duplex, 4-

wire serial interface (see Operating Sequence). The shift

clock (SCLK) synchronizes the data transfer with each bit

being transmitted on the falling SCLK edge and captured

on the rising SCLK edge in both transmitting and receiving

systems. The data is transmitted and received simulta-

neously (full duplex).

Data transfer is initiated by a falling chip select (CS) signal.

After the falling CS is recognized, an 8-bit input word is

shifted into the DIN input which configures the LTC1283

for the next conversion. Simultaneously, the result of the

previous conversion is output on the DOUT line. At the end

of the data exchange the requested conversion begins

and CS should be brought high. After tCONV, the conver-

sion is complete and the results will be available on the

next data transfer cycle. As shown below, the result of

a conversion is delayed by one CS cycle from the input

word requesting it.

DIN DIN WORD 1

DIN WORD 2

DIN WORD 3

DOUT

DOUT WORD 0

DATA

TRANSFER

tCONV

A/D

CONVERSION

DOUT WORD 1

DATA

TRANSFER

tCONV

A/D

CONVERSION

DOUT WORD 2

LTC1283 • AI02

2. Input Data Word

The LTC1283 8-bit input data word is clocked into the DIN

input on the first eight rising SCLK edges after chip select

is recognized. Further inputs on the DIN pin are then

ignored until the next CS cycle. The eight bits of the input

word are defined as follows:

DATA INPUT (DIN) WORD:

UNIPOLAR/

BIPOLAR

SGL/

DIFF

ODD/ SELECT SELECT

SIGN

1

0

UNI

MSBF

WORD

LENGTH

WL1

WL0

MUX ADDRESS

MSB-FIRST/

LSB-FIRST

LTC1283 • AI03

Operating Sequence

(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 10-Bit Word Length)

SCLK

CS

DIN

tCYC

1 2 3 4 5 6 7 8 9 10

tSMPL

DON’T CARE

tCONV

ODD/

SEL

SGL/ SIGN SEL 0

MSBF

WL0

DIFF

1

UNI

WL1

DON’T CARE

DOUT

8

SHIFT CONFIGURATION

WORD IN

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

(SB)

SHIFT A/D RESULT OUT AND

NEW CONFIGURATION WORD IN

LTC1283 • AI01

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