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EL4511 Datasheet PDF : 24 Pages
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EL4511
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS to GND) +6V
Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V, VS +0.3V
VCCA1, VCCA2 & VCCD . . . . . . . . . . . . . . . .Must Be Same Voltage
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25°C, NTSC input signal on SYNCIN, no output loads, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
ISD
Digital Supply Current
(Note 1)
15
20
mA
ISA2
ISA1
Rate Acquisition Oscillator Supply
Current
Analog Processing Supply Current
Standby PDWN = VCCD (Note 2)
(Note 1)
Standby PDWN = VCCD
(Note 1)
4
20
µA
3
20
mA
2.5
20
µA
3
20
mA
COMPOSITE SYNC INPUT AT SYNCIN
Standby PDWN = VCCD (Note 2)
3
20
µA
VSYNC
Sync Signal Amplitude
AC coupled to SYNCIN pin (Notes 1 & 3)
140
VSLICE
Slicing Level of Sync Signal
After sync lock is attained, see description
HORIZONTAL AND VERTICAL INPUT AT HIN, VERTIN
HSLICE, VSLICE Slice Level of HIN and VERTIN
THINL
H Sync Width
3
(Bi-Level)
600
mV
50
%
1.4
V
12.8
% of H
time
(Tri-Level)
Minimum Sync Width
1.4
% of H
time
FHINH
H Sync Frequency
TVINL
V Sync Width
FVINH
V Sync Frequency
LOGIC OUTPUT SIGNALS, HOUT, VOUT, VBLANK, BACKPORCH, ODD/EVEN, SYNCLOCK
O/PLOW
Logic Low State
1.6mA, VCCD = 5V
1.6mA, VCCD = 3.3V
O/PHI
Logic High State
1.6mA, VCCD = 5V
1.6mA, VCCD = 3.3V
TdHOUT
HOUT Timing Relative to Input
See timing diagrams 1, 2, 3 & 4
TdSYNCOUT
SYNCOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4
TdBACKPORCH BACKPORCH Timing Relative to
Input
See timing diagrams 1, 2, 3 & 4
10.75
2
23
VCCD-0.4
VCCD-0.5
150
kHz
7
H lines
100
Hz
GNDD+0.4 V
GNDD+0.5
V
LEVEL OUTPUT DRIVER, LEVEL
VLEVEL
ZLEVEL
2 X Amplitude of VSYNC
O/P Resistance of Driver Stage
Refer to description of operation
1.9x
2.15x
2.4x
450
Ω
2
FN7009.7
July 21, 2005
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