EL4511CU-T7 Ver la hoja de datos (PDF) - Intersil
Número de pieza
componentes Descripción
Lista de partido
EL4511CU-T7 Datasheet PDF : 24 Pages
| |||
EL4511
Pin Descriptions
PIN NUMBER
1
2
3
PIN NAME
XTAL
VBLANK
SYNCLOCK
4
PWDN
5
SDENB
6
SCL
7
SDA
8
GNDD1
9
HIN
10
SYNCIN
11
VERTIN
12
LEVEL
13
GNDA1
14
VCCA1
15
VCCA2
16
GNDA2
17
GNDD2
18
VCCD1
19
SYNCOUT
20
BACKPORCH
21
HOUT
22
VERTOUT
23
ODD/EVEN
24
XTALN
PIN TYPE
Input
Logic Output
Logic Output
Logic Input
Logic Input
Logic Input
Logic BIDIR
Power
Input
Input
Input
Output
Power
Power
Power
Power
Power
Power
Logic Output
Logic Output
Logic Output
Logic Output
Logic Output
Output
PIN DESCRIPTION
Crystal input (see Table 2 for details)
Vertical blank output
Indicates that the EL4511 has locked to the line rate and has found three consecutive
“good H lines”
Power-down = hi
Serial interface enable = low
Serial clock
Serial data (input for chip setup, output for diagnostic information)
Digital ground 1
Horizontal sync
Video input, which may incorporate sync signal; connect to Y or G
Vertical sync input
Indicates 2x amplitude of sync tip vs. back porch; referred to ground
Analog ground 1
Analog power supply 1
Analog power supply 2
Analog ground 2
Digital ground 2
Digital power supply 1
Composite sync output
Back porch output
Horizontal sync output
Vertical sync output
Odd-Even field indicator output
Crystal output (see Table 2 for details)
Typical Performance Curves
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.4
1.2 1.136W
1
0.8
θJA =8Q8S°CO/PW24
0.6
0.4
0.2
0
0
25 50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
1.2
1
870mW
0.8
0.6
θJA =1Q1S5°OCP/W24
0.4
0.2
0
0
25 50 75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
4
FN7009.7
July 21, 2005
Share Link: 