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EM638325

2M x 32Sy nchronous DRAM (SDRAM)

Etron Technology 

EtronTech

2Mega x 32 SDRAM EM638325

7 Write and AutoPrecharge command (refer to the following figure)

(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after

the write operation. Once this command is given, any subsequent command can not occur within a

time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is

performed in this command and the auto precharge function is ignored.

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND

Bank A

Activate

CAS# latency=2

tCK2, DQ's

CAS# latency=3

tCK3, DQ's

NOP

NOP

Write A

AutoPrecharge

NOP

DIN A0

DIN A1

DIN A0

DIN A1

NOP

tDAL

*

*

NOP

tDAL

NOP

NOP

tDAL= tWR + tRP

* Begin AutoPrecharge

Bank can be reactivated at completion of tDAL

Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)

8 Mode Register Set command

(RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A10-A0 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The

Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst

Length in the Mode register to make SDRAM useful for a variety of different applications. The default

values of the Mode Register after power-up are undefined; therefore this command must be issued

at the power-up sequence. The state of pins BS0,1 and A10~A0 in the same cycle is the data written

to the mode register. One clock cycle is required to complete the write in the mode register (refer to

the following figure). The contents of the mode register can be changed using the same command

and the clock cycle requirements during operation as long as all banks are in the idle state.

Preliminary

11

Rev 1.4

Oct. 2005

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