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EM83053A/BH
KEYBOARD ENCODER
TIMING DIAGRAMS
CLK
DATA
1ST
CLK
2nd
CLK
T3
T1
Start Bit
T4
T2
Bit 0
10th
CLK
11th
CLK
T5
Parity Bit
Stop Bit
Fig 3. Keyboard output data timings
CLK
I/O
Inhibit
1ST
CLK
T3 T4
T6
Start Bit
Bit 0
DATA
2nd
CLK
9th
CLK
10th
CLK
11th
CLK
Parity Bit Stop Bit
Fig 4. Keyboard input data timings
* This specification are subject to be changed without notice.
6.9.2000 18