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ENC28J60T

Stand-Alone Ethernet Controller with SPI Interface

Microchip Technology 

ENC28J60

3.1.1 ECON1 REGISTER

The ECON1 register, shown in Register 3-1, is used to

control the main functions of the ENC28J60. Receive

enable, transmit request, DMA control and bank select

bits can all be found in ECON1.

REGISTER 3-1: ECON1: ETHERNET CONTROL REGISTER 1

R/W-0

TXRST

bit 7

R/W-0

RXRST

R/W-0

DMAST

R/W-0

CSUMEN

R/W-0

TXRTS

R/W-0

RXEN

R/W-0

BSEL1

R/W-0

BSEL0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1-0

TXRST: Transmit Logic Reset bit

1 = Transmit logic is held in Reset

0 = Normal operation

RXRST: Receive Logic Reset bit

1 = Receive logic is held in Reset

0 = Normal operations

DMAST: DMA Start and Busy Status bit

1 = DMA copy or checksum operation is in progress

0 = DMA hardware is Idle

CSUMEN: DMA Checksum Enable bit

1 = DMA hardware calculates checksums

0 = DMA hardware copies buffer memory

TXRTS: Transmit Request to Send bit

1 = The transmit logic is attempting to transmit a packet

0 = The transmit logic is Idle

RXEN: Receive Enable bit

1 = Packets which pass the current filter configuration will be written into the receive buffer

0 = All packets received will be ignored

BSEL1:BSEL0: Bank Select bits

11 = SPI accesses registers in Bank 3

10 = SPI accesses registers in Bank 2

01 = SPI accesses registers in Bank 1

00 = SPI accesses registers in Bank 0

© 2006 Microchip Technology Inc.

Preliminary

DS39662B-page 15

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