ENC28J60T Ver la hoja de datos (PDF) - Microchip Technology
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ENC28J60T Datasheet PDF : 96 Pages
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ENC28J60
Stand-Alone Ethernet Controller with SPI Interface
Ethernet Controller Features
• IEEE 802.3 compatible Ethernet controller
• Integrated MAC and 10BASE-T PHY
• Supports one 10BASE-T port with automatic
polarity detection and correction
• Supports Full and Half-Duplex modes
• Programmable automatic retransmit on collision
• Programmable padding and CRC generation
• Programmable automatic rejection of erroneous
packets
• SPI Interface with clock speeds up to 20 MHz
Buffer
• 8-Kbyte transmit/receive packet dual port SRAM
• Configurable transmit/receive buffer size
• Hardware-managed circular receive FIFO
• Byte-wide random and sequential access with
auto-increment
• Internal DMA for fast data movement
• Hardware assisted checksum calculation for vari-
ous network protocols
Medium Access Controller (MAC)
Features
• Supports Unicast, Multicast and Broadcast
packets
• Programmable receive packet filtering and
wake-up host on logical AND or OR of the
following:
- Unicast destination address
- Multicast address
- Broadcast address
- Magic Packet™
- Group destination addresses as defined by
64-bit hash table
- Programmable pattern matching of up to
64 bytes at user-defined offset
Physical Layer (PHY) Features
• Loopback mode
• Two programmable LED outputs for LINK, TX,
RX, collision and full/half-duplex status
Operational
• Six interrupt sources and one interrupt output pin
• 25 MHz clock input requirement
• Clock out pin with programmable prescaler
• Operating voltage of 3.1V to 3.6V (3.3V typical)
• 5V tolerant inputs
• Temperature range: -40°C to +85°C Industrial,
0°C to +70°C Commercial (SSOP only)
• 28-pin SPDIP, SSOP, SOIC, QFN packages
Package Types
28-Pin SPDIP, SSOP, SOIC
VCAP
1
28
VSS
2
27
CLKOUT
3
26
INT
4
25
NC*
5
24
SO
6
23
SI
7
22
SCK
8
21
CS
9
20
RESET
10
19
VSSRX
11
18
TPIN-
12
17
TPIN+
13
16
RBIAS
14
15
VDD
LEDA
LEDB
VDDOSC
OSC2
OSC1
VSSOSC
VSSPLL
VDDPLL
VDDRX
VSSTX
TPOUT+
TPOUT-
VDDTX
28-pin QFN
NC*
SO
SI
SCK
CS
RESET
VSSRX
28 27 26 25 24 23 22
1
21
2
20
3
19
4 ENC28J60 18
5
17
6
16
7
15
8 9 10 11 12 13 14
VDDOSC
OSC2
OSC1
VSSOSC
VSSPLL
VDDPLL
VDDRX
* Reserved pin; always leave disconnected.
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 1
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