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FDC37C672TQFP Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
8.4 Enhanced DUMPREG................................................................................................................................61
8.5 Compatibility...............................................................................................................................................62
Chapter 9 Serial Port (UART) ............................................................................................................... 63
9.1 Register Description ...................................................................................................................................63
9.1.1 Receive Buffer Register (RB) ..............................................................................................................64
9.1.2 Transmit Buffer Register (TB) .............................................................................................................64
9.1.3 Interrupt Enable Register (IER) ...........................................................................................................64
9.1.4 FIFO Control Register (FCR) ..............................................................................................................65
9.1.5 Interrupt Identification Register (IIR) ...................................................................................................65
9.1.6 Line Control Register (LCR) ................................................................................................................67
9.1.7 Modem Control Register (MCR)..........................................................................................................68
9.1.8 Line Status Register (LSR) .................................................................................................................69
9.1.9 Modem Status Register (MSR) ...........................................................................................................71
9.1.10 Scratchpad Register (SCR) .............................................................................................................72
9.2 Programmable Baud Rate Generator (and Divisor Latches DLH, DLL) .....................................................72
9.2.1 Effect Of The Reset on Register File...................................................................................................72
9.3 FIFO Interrupt Mode Operation ..................................................................................................................72
9.4 FIFO Polled Mode Operation .....................................................................................................................73
9.5 Notes on Serial Port Operation ..................................................................................................................76
9.5.1 FIFO Mode Operation: ........................................................................................................................76
Chapter 10 Infrared Interface .................................................................................................................. 78
Chapter 11 Fast IR .................................................................................................................................. 79
Chapter 12 Parallel Port.......................................................................................................................... 80
12.1 IBM XT/AT Compatible, Bi-Directional and EPP Modes .........................................................................81
12.2 Extended Capabilities Parallel Port.........................................................................................................87
12.2.1 Vocabulary.......................................................................................................................................87
12.3 ISA Implementation Standard.................................................................................................................88
12.3.1 Register Definitions .........................................................................................................................90
12.4 Operation................................................................................................................................................96
12.4.1 Mode Switching/Software Control....................................................................................................96
12.4.2 Data Compression...........................................................................................................................97
12.4.3 Pin Definition ...................................................................................................................................97
12.4.4 ISA Connections..............................................................................................................................97
12.4.5 Interrupts .........................................................................................................................................98
12.4.6 FIFO Operation................................................................................................................................98
12.5 DMA Transfers........................................................................................................................................98
12.5.1 Programmed I/O Mode or Non-DMA Mode .....................................................................................99
12.5.2 Programmed I/O - Transfers from the FIFO to the Host ..................................................................99
12.5.3 Programmed I/O - Transfers from the Host to the FIFO ................................................................100
12.6 Parallel Port Floppy Disk Controller ......................................................................................................100
Chapter 13 Auto Power Management................................................................................................... 102
Chapter 14 Serial IRQ........................................................................................................................... 106
14.1 Serial Interrupts ....................................................................................................................................106
14.1.1 Timing Diagrams For IRQSER Cycle ............................................................................................106
14.1.2 IRQSER Cycle Control ..................................................................................................................107
14.1.3 IRQSER Data Frame.....................................................................................................................108
14.1.4 Stop Cycle Control.........................................................................................................................108
14.1.5 Latency ..........................................................................................................................................109
14.1.6 EOI/ISR Read Latency ..................................................................................................................109
14.1.7 AC/DC Specification Issue ............................................................................................................109
14.1.8 Reset and Initialization ..................................................................................................................109
Chapter 15 GP Index Registers ............................................................................................................ 110
Chapter 16 Watch Dog Timer ............................................................................................................... 111
Chapter 17 8042 Keyboard Controller Description ............................................................................... 112
17.1 Keyboard ISA Interface.........................................................................................................................112
17.1.1 Keyboard Data Write .....................................................................................................................113
17.1.2 Keyboard Data Read .....................................................................................................................113
17.1.3 Keyboard Command Write ............................................................................................................113
17.1.4 Keyboard Status Read ..................................................................................................................113
SMSC FDC37C672
Page 5
PRELIMINARY DATASHEET
Rev. 10-29-03
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