FDC37M81X Ver la hoja de datos (PDF) - SMSC -> Microchip

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FDC37M81X

PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up

SMSC -> Microchip 

Description of Multifunction Pins

PIN

ORIGINAL ALTERNATE

NO./QFP FUNCTION FUNCTION 1

51

nDACK3

8042 P16

52

DRQ3

8042 P12

92

nRI2

8042 P16

94

nDCD2

8042 P12

95

RXD2

IRRX

96

TXD2

IRTX

97

nDSR2

SA15

98

nRTS2

SA12

99

nCTS2

SA13

100 nDTR2

SA14

Note 1: Controlled by DMA3SEL(LD8:CRC0.1)

Note 2: Controlled by 8042COMSEL(LD8:CRC0.3)

Note 3: Controlled by IR Option Register( LD5:CRF1.6)

Note 4: Controlled by 16 bit Address Qualification (CR24.6)

DEFAULT

nDACK3

DRQ3

nRI2

nDCD2

RXD2

TXD2

nDSR2

nRTS2

nCTS2

nDTR2

NOTE

1

1

2

2

3

3

4

4

4

4

For more information, refer to tables 63 through 73.

REFERENCE DOCUMENTS

1. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.

2. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.

3. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997.

10

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