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AD8522AR-REEL

+5 Volt, Serial Input, Dual 12-Bit DAC

Analog Devices 

AD8522–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS (@ VDD = +5.0 V ؎ 10%, RL = No Load, –40؇C ≤ TA ≤ +85؇C, both DACs tested, unless

otherwise noted)

Parameter

Symbol Condition

Min Typ Max Units

STATIC PERFORMANCE

Resolution1

Relative Accuracy

Differential Nonlinearity

Zero-Scale Error

Full-Scale Voltage2

Full-Scale Tempco2, 3

MATCHING PERFORMANCE

Linearity Matching Error

ANALOG OUTPUT

Output Current

Load Regulation at Half-Scale

Capacitive Load3

REFERENCE OUTPUT

Output Voltage

Output Source Current4

Line Rejection

Load Regulation

LOGIC INPUTS & OUTPUTS

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current

Input Capacitance3

Logic Output Voltage Low

Logic Output Voltage High

TIMING SPECIFICATIONS3, 5

Clock Width High

Clock Width Low

Load Pulse Width

Data Setup

Data Hold

Clear Pulse Width

Load Setup

Load Hold

Select

Deselect

Clock to SDO Propagation Delay

AC CHARACTERISTICS3, 5

Voltage Output Settling Time6

Crosstalk

N

INL

DNL

VZSE

VFS

TCVFS

∆VFSA/B

IOUT

LDREG

CL

VREF

IREF

LNREJ

LDREG

VIL

VIH

IIL

CIL

VOL

VOH

tCH

tCL

tLDW

tDS

tDH

tCLRW

tLD1

tLD2

tCSS

tCSH

tPD

tS

CT

DAC Glitch

Q

Digital Feedthrough

DFT

Monotonic

Data = 000H

Data = FFFH

Data = 800H, ∆VOUT ≤ 3 LSB

RL = 402 Ω to ∞, Data = 800H

No Oscillation

∆VREF < 18 mV

IREF = 0 to 5 mA, Data = 800H

IOL = 1.6 mA

IOH = 400 µA

To ± 1 LSB of Final Value

Signal Measured at DAC Output,

While Changing Opposite LDA/B

Half-Scale Transition

Signal Measured at DAC Output,

While Changing Data Without LDA/B

12

-1.5

-1

4.079

± 0.5

± 0.5

+0.5

4.095

± 15

+1.5

+1

+3

4.111

Bits

LSB

LSB

mV

Volts

ppm/°C

±1

LSB

±5

mA

1

3

LSB

500

pF

2.484

2.500

0.025

0.025

2.516

5

0.08

0.1

V

mA

%/V

%/mA

0.8 V

2.4

V

10

µA

10

pF

0.4 V

3.5

V

35

ns

35

ns

25

ns

10

ns

20

ns

20

ns

10

ns

10

ns

30

ns

30

ns

20

45

80

ns

16

µs

38

dB

13

nV s

2

nV s

SUPPLY CHARACTERISTICS

Positive Supply Current

Power Dissipation7

Power Supply Sensitivity

IDD

PDISS

PSS

VDD = 5.5 V, VIH = 2.4 V or VIL = 0.8 V

VDD = 5 V, VIL = 0 V

VDD = 5 V, VIH = 2.4 V or VIL = 0.8 V

VDD = 5 V, VIL = 0 V

∆VDD = ± 5%

3

1

15

5

0.002

5

2

25

10

0.004

mA

mA

mW

mW

%/%

NOTES

11 LSB = 1 mV for 0 V to +4.095 V output range.

2Includes internal voltage reference error.

3These parameters are guaranteed by design and not subject to production testing.

4Very little sink current is available at the VREF pin. Use external buffer if setting up a virtual ground.

5All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.

7Power Dissipation is calculated IDD × 5 V.

Specifications subject to change without notice.

–2–

REV. A

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