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FS6377 Datasheet PDF : 24 Pages
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FS6377
5.1.5. Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must
generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the
high period of the master acknowledge clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked)
out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
5.2 I2C-bus Operation
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The device
accepts the following I2C-bus commands.
5.2.1. Slave Address
After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the
device is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
X
0
0
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different devices to exist on the same bus. Note that every device on an I2C-bus must have a unique
address to avoid bus conflicts. The default address sets A2 to one via the pull-up on the ADDR pin.
5.2.2. Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted
after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the
slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an
acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned
by the device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
5.2.3. Random Register Read Procedure
Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device
that a register address will follow after the slave device acknowledges its device address. The register address is then written into the
slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write
procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a
logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit
word. The master does not acknowledge the transfer but does generate a STOP condition.
5.2.4. Sequential Register Write Procedure
Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after
each write. This procedure is more efficient than the random register write if several registers must be written.
To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the
addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address
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