GS1560A(2007) Ver la hoja de datos (PDF) - Gennum -> Semtech
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GS1560A Datasheet PDF : 80 Pages
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1.3 Pin Descriptions
GS1560A/GS1561 Data Sheet
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type Description
1
CP_VDD
–
Power Power supply connection for the charge pump. Connect to +3.3V DC
analog.
2
PDBUFF_GND
–
Power Ground connection for the phase detector and serial digital input buffers.
Connect to analog GND.
3
PD_VDD
–
Power Power supply connection for the phase detector. Connect to +1.8V DC
analog.
4
BUFF_VDD
–
Power Power supply connection for the serial digital input buffers. Connect to
+1.8V DC analog.
5
CD1
Non
Input STATUS SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI1 and DDI1
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
6, 8
DDI1, DDI1
Analog
Input Differential input pair for serial digital input 1.
7
TERM1
Analog
Input Termination for serial digital input 1. AC couple to EQ_GND.
9
DVB_ASI
Non
Input / CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Synchronous Output Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The DVB_ASI signal will be HIGH only when the device has locked to a
DVB-ASI compliant data stream. It will be LOW otherwise.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS
= LOW, the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the decoding or word alignment
of received DVB-ASI data.
10
IP_SEL
Non
Input CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input signal,
and CD1 or CD2 as the carrier detect input signal.
When set HIGH, DDI1 / DDI1 is selected as the serial digital input and
CD1 is selected as the carrier detect input signal.
When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect
input signal is selected.
27360 - 10 January 2007
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