GS1560ACF Ver la hoja de datos (PDF) - Gennum -> Semtech
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GS1560ACF Datasheet PDF : 79 Pages
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
21
22
23, 24
25
Name
SDO_EN/DIS
NC
CD_GND
NC
SDO, SDO
NC
RESET_TRST
Timing
Type Description
Non
Synchronous
Input
GS1560A
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
–
–
GS1561
No Connect.
–
Power GS1560A
Ground connection for the serial digital cable driver. Connect to
analog GND.
–
–
GS1561
No Connect.
Analog
Output
GS1560A
Serial digital loop-through output signal operating at 1.485Gb/s,
1.485/1.001Gb/s, or 270Mb/s.
The slew rate of these outputs is automatically controlled to meet
SMPTE 292M and 259M specifications according to the setting of the
SD/HD pin.
–
–
GS1561
No Connect.
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and
to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default
conditions and all input and output signals become high impedance,
including the serial digital outputs SDO and SDO.
Must be set HIGH for normal device operation.
NOTE: When in slave mode, reset the device after the SD/HD input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and
the JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer
Data Sheet
27360 - 12
June 2009
11 of 79
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