GS1582(2007) Ver la hoja de datos (PDF) - Gennum -> Semtech

Número de pieza

componentes Descripción

Lista de partido

GS1582
(Rev.:2007)

Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner™

Gennum -> Semtech 

GS1582 Data Sheet

Table 1-1: Pin Descriptions (Continued)

Pin

Number

Name

Timing

Type Description

B4

B5, C5, D5,

E2, E5, E6,

E7, F5, F6,

F7, G9, J8

C6, C7, C8

B7

B8, B9

B10

C4

C9, D9, E9,

F9

C10, D10

PCLK

CORE_GND

PD_GND

CP_RES

VCO_GND

CP_GND

V/VSYNC

CD_GND

SDO, SDO

–

Non

Synchronous

Input

Input

Power

PARALLEL DATA BUS CLOCK

Signal levels are LVCMOS/LVTTL compatible.

HD 20-bit mode

PCLK = 74.25MHz or 74.25/1.001MHz

HD 10-bit mode

PCLK = 148.5MHz or 148.5/1.001MHz

SD 20-bit mode

PCLK = 13.5MHz

SD 10-bit mode

PCLK = 27MHz

Ground connection for the digital core logic. Connect to digital GND.

Analog

–

Analog

Analog

Synchronous

with PCLK

Analog

Analog

Input

Power

Input

Output

Power

Input

Power

Input

Input

Power

Output

Ground connection for the phase detector. Connect to analog GND.

Charge pump current setting resistor.

Ground pins for the VCO.

Ground pin for the charge pump and PLL.

PARALLEL DATA TIMING

Signal levels are LVCMOS/LVTTL compatible.

TIM_861 = LOW:

The V signal is used to indicate the portion of the video field/frame that

is used for vertical blanking, when DETECT_TRS is set LOW.

The V signal should be set HIGH for the entire vertical blanking period

and should be set LOW for all lines outside of the vertical blanking

interval.

The V signal is ignored when DETECT_TRS = HIGH.

TIM_861 = HIGH:

The VSYNC signal indicates vertical timing. See Section 4.3.1 for timing

details.

The VSYNC signal is ignored when DETECT_TRS = HIGH.

Ground connection for the serial digital cable driver. Connect to analog

GND.

Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or

270Mb/s.

The slew rate of these outputs is automatically controlled to meet

SMPTE 292M and 259M requirements according to the setting of the

SD/HD pin.

Serial digital output signal from the internal cable driver.

NOTE: The SDO/SDO output signals will be set to high impedance

when RESET = LOW.

40117 - 1 November 2007

10 of 114

Share Link: