GS71108AGJ-10 Ver la hoja de datos (PDF) - Unspecified

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GS71108AGJ-10

128K x 8 1Mb Asynchronous SRAM

Unspecified 

GS71108ATP/J/SJ/U

AC Test Conditions

Parameter

Conditions

Input high level

Input low level

Input rise time

Input fall time

Input reference level

Output reference level

Output load

VIH = 2.4 V

VIL = 0.4 V

tr = 1 V/ns

tf = 1 V/ns

1.4 V

1.4 V

Fig. 1& 2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ

Output Load 1

DQ

50Ω 30pF1

VT = 1.4 V

Output Load 2

3.3 V

DQ

589Ω

5pF1 434Ω

AC Characteristics

Read Cycle

Parameter

Read cycle time

Address access time

Chip enable access time (CE)

Output enable to output valid (OE)

Output hold from address change

Chip enable to output in low Z (CE)

Output enable to output in low Z (OE)

Chip disable to output in High Z (CE)

Output disable to output in High Z (OE)

Symbol

tRC

tAA

tAC

tOE

tOH

tLZ*

tOLZ*

tHZ*

tOHZ*

-7

Min Max

7

—

—

7

—

7

—

3

3

—

3

—

0

—

—

3.5

—

3

* These parameters are sampled and are not 100% tested

-8

Min Max

8

—

—

8

—

8

—

3.5

3

—

3

—

0

—

—

4

—

3.5

-10

Min Max

10 —

— 10

— 10

—

4

3

—

3

—

0

—

—

5

—

4

-12

Unit

Min Max

12 — ns

— 12 ns

— 12 ns

—

5

ns

3

— ns

3

— ns

0

— ns

—

6

ns

—

5

ns

Rev: 1.08 6/2006

5/16

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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