HB52RD649DC Ver la hoja de datos (PDF) - Elpida Memory, Inc

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HB52RD649DC

512MB Unbuffered SDRAM S.O.DIMM

Elpida Memory, Inc 

HB52RF649DC-B, HB52RD649DC-B

Notes: 1. AC measurement assumes tT = 1ns. Reference level for timing of input signals is 1.5V.

2. Access time is measured at 1.5V. Load condition is CL = 50pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

5. tCES defines CKE setup time to CK rising edge except power down exit command.

Test Conditions

• Input and output timing reference levels: 1.5V

• Input waveform and output load: See following figures

input

2.4V

2.0V

0.4V 0.8V

I/O

CL

tT

tT

Input waveform and output load

Data Sheet E0223H30 (Ver. 3.0)

11

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