H8/36037F Ver la hoja de datos (PDF) - Renesas Electronics
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H8/36037F Datasheet PDF : 592 Pages
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3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 55
3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 55
3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 57
3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 57
3.3 Reset Exception Handling .................................................................................................. 59
3.4 Interrupt Exception Handling ............................................................................................. 60
3.4.1 External Interrupts .............................................................................................. 60
3.4.2 Internal Interrupts ............................................................................................... 61
3.4.3 Interrupt Handling Sequence .............................................................................. 62
3.4.4 Interrupt Response Time..................................................................................... 63
3.5 Usage Notes ........................................................................................................................ 65
3.5.1 Interrupts after Reset........................................................................................... 65
3.5.2 Notes on Stack Area Use .................................................................................... 65
3.5.3 Notes on Rewriting Port Mode Registers ........................................................... 65
Section 4 Address Break ..................................................................................... 67
4.1 Register Descriptions.......................................................................................................... 68
4.1.1 Address Break Control Register (ABRKCR) ..................................................... 68
4.1.2 Address Break Status Register (ABRKSR) ........................................................ 70
4.1.3 Break Address Registers (BARH, BARL).......................................................... 70
4.1.4 Break Data Registers (BDRH, BDRL) ............................................................... 70
4.2 Operation ............................................................................................................................ 71
Section 5 Clock Pulse Generators ....................................................................... 73
5.1 System Clock Generator ..................................................................................................... 74
5.1.1 Connecting Crystal Resonator ............................................................................ 74
5.1.2 Connecting Ceramic Resonator .......................................................................... 75
5.1.3 External Clock Input Method.............................................................................. 75
5.2 Prescaler.............................................................................................................................. 76
5.2.1 Prescaler S .......................................................................................................... 76
5.3 Usage Notes ........................................................................................................................ 76
5.3.1 Note on Resonators............................................................................................. 76
5.3.2 Notes on Board Design ....................................................................................... 76
Section 6 Power-Down Modes............................................................................ 77
6.1 Register Descriptions.......................................................................................................... 78
6.1.1 System Control Register 1 (SYSCR1) ................................................................ 78
6.1.2 System Control Register 2 (SYSCR2) ................................................................ 79
6.1.3 Module Standby Control Register 1 (MSTCR1) ................................................ 80
6.1.4 Module Standby Control Register 2 (MSTCR2) ................................................ 81
Rev. 4.00 Mar. 15, 2006 Page x of xxxii
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