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H8/36037

Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Renesas Electronics 

Contents

Section 1 Overview................................................................................................1

1.1 Features................................................................................................................................. 1

1.2 Internal Block Diagram......................................................................................................... 3

1.3 Pin Arrangement ................................................................................................................... 4

1.4 Pin Functions ........................................................................................................................ 5

Section 2 CPU........................................................................................................9

2.1 Address Space and Memory Map ....................................................................................... 10

2.2 Register Configuration........................................................................................................ 14

2.2.1 General Registers................................................................................................ 15

2.2.2 Program Counter (PC) ........................................................................................ 16

2.2.3 Condition-Code Register (CCR)......................................................................... 16

2.3 Data Formats....................................................................................................................... 18

2.3.1 General Register Data Formats ........................................................................... 18

2.3.2 Memory Data Formats ........................................................................................ 20

2.4 Instruction Set ..................................................................................................................... 21

2.4.1 Table of Instructions Classified by Function ...................................................... 21

2.4.2 Basic Instruction Formats ................................................................................... 31

2.5 Addressing Modes and Effective Address Calculation....................................................... 32

2.5.1 Addressing Modes .............................................................................................. 32

2.5.2 Effective Address Calculation ............................................................................ 36

2.6 Basic Bus Cycle .................................................................................................................. 38

2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 38

2.6.2 On-Chip Peripheral Modules .............................................................................. 39

2.7 CPU States .......................................................................................................................... 40

2.8 Usage Notes ........................................................................................................................ 42

2.8.1 Notes on Data Access to Empty Areas ............................................................... 42

2.8.2 EEPMOV Instruction.......................................................................................... 42

2.8.3 Bit-Manipulation Instruction .............................................................................. 42

Section 3 Exception Handling .............................................................................49

3.1 Exception Sources and Vector Address .............................................................................. 50

3.2 Register Descriptions.......................................................................................................... 52

3.2.1 Interrupt Edge Select Register 1 (IEGR1) .......................................................... 52

3.2.2 Interrupt Edge Select Register 2 (IEGR2) .......................................................... 53

3.2.3 Interrupt Enable Register 1 (IENR1) .................................................................. 54

Rev. 4.00 Mar. 15, 2006 Page ix of xxxii

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