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HD74HC597

8-bit Latch/Shift Register

Hitachi -> Renesas Electronics 

HD74HC597

8-bit Latch/Shift Register

Description

The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both

the storage register and shift register have positive-edge triggered clocks. The shift register also has direct

load (from storage) and clear inputs.

Features

• High Speed Operation: tpd (SCK to QH’) = 14 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Function Table

RCK

X

X

SCK

X

X

X

X

SLoad

X

L

L

L

SCLR

X

H

H

L

X

X

H

L

X

H

H

Function

Data loaded to input latches

Data loaded from inputs to shift register

Data transferred from input latches to shift register

Invalid logic, state of shift register indeterminate when signals

removed

Shift register cleared

Shift register clocked Qn = Qn – 1, QA = SER

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