HD74HCT564 Ver la hoja de datos (PDF) - Renesas Electronics
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HD74HCT564 Datasheet PDF : 9 Pages
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HD74HCT564, HD74HCT574
Octal D-type Flip-Flops (with 3-state outputs)
REJ03D0670–0200
(Previous ADE-205-560)
Rev.2.00
Mar 30, 2006
Description
These devices are positive edge triggered flip-flops. The difference between HD74HCT564 and HD74HCT574 is only
that the former has inverting outputs and the latter has noninvertering outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive
going transitions of the clock (CK) input. when a high logic level is applied to the output control (OC) input, all outputs
go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HCT564P
HD74HCT574P
DILP-20 pin
PRDP0020AC-B
P
(DP-20NEV)
HD74HCT564FPEL
HD74HCT574FPEL
SOP-20 pin (JEITA)
PRSP0020DD-B
(FP-20DAV)
FP
HD74HCT564RPEL
HD74HCT574RPEL
SOP-20 pin (JEDEC)
PRSP0020DC-A
(FP-20DBV)
RP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Function Table
Inputs
Outputs
Output Control
Clock
Data
HD74HCT564
HD74HCT574
L
H
L
H
L
L
H
L
L
L
X
Q0
Q0
H
X
X
Z
Z
Q0 : level of Q before the indicated Steady-sate input conditions were established.
Q0 : complement of Q0 or level of Q before the indicated Steady-state input Conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 8
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