HDM8515 Ver la hoja de datos (PDF) - Hynix Semiconductor

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HDM8515

DVB/DSS Compliant Receiver

Hynix Semiconductor 

Table 3: Demodulator Specifications

Parameter

Sampling Clock Frequency

Analog Input Full Scale Range

Symbol Rate

Viterbi Data Rate

Reed Solomon Data Rate

Implementation Loss

Symbol Rate Resolution

Carrier Frequency Resolution

Acquisition Sweep Range

Min.

1MHz

0.9 Vpp

1Msps

-

-

-

Clock/(220)

Clock/(2 )20

-

Max.

90MHz

1.1 Vpp

66Msps

90Mbps

82Mbps

0.5 dB

-

-

+ or - Clock/2

Table 4: AC Characteristics

Symbol

Parameter

Min.

tsu1

Input Data Setup before Clock

6

th1

Input Data Hold after Clock

2

tpw1 Low Pulse Width of Clock

8.7

tpw2 High Pulse Width of Clock

8.1

CLOCK

I_IN [5:0]

or Q_IN [5:0]

tpw1

tpw2

tsu1 th1

Max.

Unit

-

ns

-

ns

-

ns

-

ns

FIGURE 2: INPUT DATA TIMING DIAGRAM

10

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