HDMP-1032A Ver la hoja de datos (PDF) - HP => Agilent Technologies

Número de pieza

componentes Descripción

Lista de partido

HDMP-1032A

Transmitter/Receiver Chip Set

HP => Agilent Technologies 

REFCLK. This feature is particu-

larly useful when the Tx clock

and REFCLK are synchronous.

The PASS system also supports

synchronization of multiple

channels.

The chipset is compatible with

previous versions of the G-Link

chipset (HDMP-10x2/10x4)

provided the latter are used in

16 bit Simplex with Periodic Sync

Pulse or External Reference

Oscillator Mode (Simplex Method

II or III).

Table of Contents

Topic

Page

Typical Applications ................................................................................................... 3

Setting the Operating Data Rate Range .................................................................. 4

Transmitter Block Diagram ....................................................................................... 5

Receiver Block Diagram ............................................................................................ 6

Parallel Automatic Synchronization System .......................................................... 7

Transmitter Timing .................................................................................................... 10

Receiver Timing ........................................................................................................... 11

DC Electrical Specifications ..................................................................................... 12

AC Electrical Specifications ..................................................................................... 12

TXCLK and REFCLK Requirements ........................................................................... 13

Absolute Maximum Ratings ...................................................................................... 13

Thermal Characteristics ............................................................................................ 14

I/O Type Definitions .................................................................................................... 14

Pin-Out Diagrams ........................................................................................................ 15

Transmitter Pin Definitions ........................................................................................ 16

Receiver Pin Definitions ............................................................................................ 18

Mechanical Dimensions ............................................................................................ 21

Appendix: Internal Architecture Information

Line Code Description ................................................................................................ 22

Data, Control, and Idle Word Codes ........................................................................ 22

Tx Operation Principles – Encoding & Phase Lock Loop .................................... 24

Rx Operation Principles – Decoding & Phase Lock Loop .................................... 25

Integrator Capacitor & Power Supply

Bypassing/Grounding ................................................................................................. 26

TTL and High Speed I/O ............................................................................................. 26

Data Bus Line/Broadcast Transmission ................................................................. 27

Nomenclature Changes between

HDMP-1032A/34A and HDMP-1022/24 .................................................................... 30

Pin Cross Reference Table ........................................................................................ 31

2

Share Link: