HI-5700 Ver la hoja de datos (PDF) - Intersil

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HI-5700

8-Bit, 20 MSPS Flash A/D Converter

Intersil 

CLOCK INPUT

50Ω

TO ANALOG +5V

OUTPUT

PINS

DIGITAL

VDD

10µF

0.01µF

TO ANALOG GND

DIGITAL

GROUND

OUTPUT

PINS

HI-5700

1 CLK

2 D7

3 D6

4 D5

5 D4

6 1/4R

7 VDD

8 GND

9 3/4R

10 D3

11 D2

12 D1

13 D0

14 OVF

100Ω

VIN 28

VREF - 27

AVDD 26

AGND 25

AGND 24

AVDD 23

1/2R 22

AVDD 21

AGND 20

AGND 19

AVDD 18

VREF + 17

CE1 16

CE2 15

+5V

HA-5033

+9V TO +12V

0.01µF

+9V TO +12V 0.01µF

0.01µF

ANALOG

GROUND

0.01µF

0.01µF

10µF

10µF

10µF

10µF

10µF

ANALOG

SIGNAL

INPUT

ANALOG

VDD (+5V)

PRECISION

DC

REFERENCE

FIGURE 15. TEST CIRCUIT

Applications Information

Voltage Reference

The reference voltage is applied across the resistor ladder

between VREF+ and VREF-. In most applications, VREF- is

simply tied to analog ground such that the reference source

drives VREF +. The reference must be capable of supplying

enough current to drive the minimum ladder resistance of

235Ω over temperature.

The HI-5700 is specified for a reference voltage of 4.0V, but

will operate with voltages as high as the VDD supply. In the

case of 4.0V reference operation, the converter encodes the

analog input into a binary output in LSB increments of

(VREF+ - VREF-)/256, or 15.6mV. Reducing the reference

voltage reduces the LSB size proportionately and thus

increases linearity errors. The minimum practical reference

voltage is about 2.5V. Because the reference voltage

terminals are subjected to internal transient currents during

conversion, it is important to drive the reference pins from a

low impedance source and to decouple thoroughly. Again,

ceramic and tantalum (0.01µF and 10µF) capacitors near

the package pin are recommended. It is not necessary to

decouple the 1/4R, 1/2R, and 3/4R tap point pins for most

applications.

It is possible to elevate VREF - from ground if necessary. In

this case, the VREF - pin must be driven from a low

impedance reference capable of sinking the current through

the resistor ladder. Careful decoupling is again

recommended.

Digital Control and Interface

The HI-5700 provides a standard high speed interface to

external CMOS and TTL logic families. Two chip enable

inputs control the three-state outputs of output bits D0

through D7 and the Overflow (OVF) bit. As indicated in the

Truth Table, all output bits are high impedance when CE2 is

low, and output bits D0 through D7 are independently

controlled by CE1.

Although the Digital Outputs are capable of handling typical

data bus loading, the bus capacitance charge/discharge

currents will produce supply and local group disturbances.

Therefore, an external bus driver is recommended.

Clock

The clock should be properly terminated to digital ground

near the clock input pin. Clock frequency defines the

conversion frequency and controls the converter as

described in the “Theory of Operation” section. The Auto

Balance φ1 half cycle of the clock may be reduced to

approximately 20ns; the Sample φ2 half cycle may be varied

from a minimum of 25ns to a maximum of 5µs.

Signal Source

A current pulse is present at the analog input (VIN) at the

beginning of every sample and auto balance period. The

transient current is due to comparator charging and switch

feedthrough in the capacitor array. It varies with the

amplitude of the analog input and the converter’s sampling

4-1499

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