HI-8582(2001) Ver la hoja de datos (PDF) - Holt Integrated Circuits
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HI-8582 Datasheet PDF : 15 Pages
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HI-8582, HI-8583
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at TXAOUT and TXBOUT. The 31 or 32 bits in
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the “1”s in the 31-bit word. If control
register bit CR12 is set low, the 32nd bit transmitted will make
parity odd. If the control bit is high, the parity is even. Setting
CR4 to a zero bypasses the parity generator, and allows 32 bits of
data to be transmitted.
SELF TEST
If control register bit CR5 is set low, the transmitter serial output
data are internally connected to each of the two receivers,
bypassing the analog interface circuitry. Data is passed
unmodified to receiver 1, and inverted to receiver 2. Taking TEST
high forces TXAOUT and TXBOUT into the null state regardless
of the state of CR5.
SYSTEM OPERATION
The two receivers are independent of the transmitter.
Therefore, control of data exchanges is strictly at the option of
the user. The only restrictions are:
1. The received data will be overwritten if the receiver FIFO
is full and at least one location is not retrieved before the next
complete ARINC word is received.
2. The transmitter FIFO can store 32 words maximum and
ignores attempts to load additional data if full.
LINE DRIVER OPERATION
The line driver in the HI-8582 is designed to directly drive the ARINC
429 bus. The two ARINC outputs (TXAOUT and TXBOUT) provide
a differential voltage to produce a +10 volt One, a -10 volt Zero,
and a 0 volt Null. Control register bit CR13 controls both the
transmitter data rate, and the slope of the differential output signal.
No additional hardware is required to control the slope.
Programming CR13 to zero causes a 100 kbits/s data rate and a
slope of 1.5 µs on the ARINC outputs; a one on CR13 causes a
12.5 kbit/s data rate and a slope of 10 µs. Timing is set by on-chip
resistor and capacitor and tested to be within ARINC requirements.
The HI-8582 has 37.5 ohms in series with each line driver output.
The 8583 has 10 ohms in series. The HI-8583 is for applications
where external series resistance is needed, typically for lightning
protection devices.
REPEATER OPERATION
Repeater mode of operation allows a data word that has been
received by the HI-8582 to be placed directly into the transmitter
FIFO. Repeater operation is similar to normal receiver operation.
In normal operation, either byte of a received data word may be
read from the receiver latches first by use of SEL input. During
repeater operation however, the lower byte of the data word must
be read first. This is necessary because, as the data is being read,
it is also being loaded into transmitter FIFO which is always loaded
with the lower byte of the data word first. Signal flow for repeater
operation is shown in the Timing Diagrams section.
HI-8582-10
The HI-8582-10 option is similar to the HI-8582 with the exception
that it allows an external 10 Kohm resistor to be added in series
with each ARINC input without affecting the ARINC input thresh-
olds. This option is especially useful in applications where lightning
protection circuitry is also required.
Each side of the ARINC bus must be connected through a
10 Kohm series resistor in order for the chip to detect the correct
ARINC levels. The typical 10 volt differential signal is translated
and input to a window comparator and latch. The comparator lev-
els are set so that with the external 10 Kohm resistors, they are
just below the standard 6.5 volt minimum ARINC data threshold
and just above the standard 2.5V maximum ARINC null threshold.
HIGH SPEED OPERATION
The HI-8582 may be operated at clock frequencies beyond that
required for ARINC compliant operation. For operation at Master
Clock (CLK) frequencies up to 5MHz, please contact Holt
applications engineering.
HOLT INTEGRATED CIRCUITS
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